Engineering wafers for the nanotechnology era

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 29-38

  Mazuré, Carlos ^a   Auberton Hervé, André Jacques ^a  

^a PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC DESIGN; MOSFET DEVICES; NANOTECHNOLOGY; OPTIMIZATION;

DEVICE ARCHITECTURE; PARASITIC ELEMENTS; SUBSTRATE DESIGN;

SILICON WAFERS;

EID: 33751421996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546579     Document Type: Conference Paper

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