CAD-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 288-289

  Ueda, Kimio ^a   Nii, Koji ^a   Wada, Yoshiki ^a   Takimoto, Isao ^a   Maeda, Shigenobu ^a   Iwamatsu, Toshiaki ^a   Yamaguchi, Yasuo ^a   Maegawa, Shigeto ^a   Mashiko, Koichiro ^a   Hamano, Hisanori ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; DELAY CIRCUITS; ELECTRIC BREAKDOWN OF SOLIDS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; POWER CONTROL; SILICON ON INSULATOR TECHNOLOGY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; VOLTAGE CONTROL;

DRAIN CURRENTS; LOGIC GATE ARRAYS;

LOGIC GATES;

EID: 0031074275     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)