A VLSI design methodology for SOI technology

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 5-8

  Allen, David H ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY POTENTIAL; PARASITIC EXTRACTION; POWER DISSIPATION; WAFER FABRICATION;

ANTENNAS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY DISSIPATION; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; NATURAL FREQUENCIES; SIMULATORS; VLSI CIRCUITS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 16244414292     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. G.Shahidi, "SOI technology for the GHz era," IBM Journal of Research and Development, pp. 121-131, March/May 2002.
2. D. Allen, et al. "Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology," 1999 Design Automation Conference, June 1999
3. M. Bhushan, International Business Machines internal correspondence, July 2004.
4. "AS/X User's Guide", International Business Machines Technical Memorandum, No. 220-5233-00, March 1994.
5. K. L. Shepard and V. Narayanan, "Noise in deep submicron digital design", in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 524-531, November 1996.
6. J. Rahmen, "3DNoise User's Guide", International Business Machines Technical Memorandum, June 1996.
7. K. Bernstein and N. Rohrer, "SOI Design Concepts," Kluwer Academic Publishers, Chapter 6, 2000.