Statistical timing based optimization using gate sizing

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 400-405

  Agarwal, Aseem ^a   Chopra, Kaviraj ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRUTE-FORCE COMPUTATION; ISCAS BENCHMARK CIRCUITS; STATISTICAL OPTIMIZERS; STATISTICAL STATIC TIMING ANALYSIS (SSTA);

ALGORITHMS; COMPUTATION THEORY; DELAY CIRCUITS; OPTIMIZATION; PERTURBATION TECHNIQUES; TIME SERIES ANALYSIS; TIMING CIRCUITS;

LOGIC CIRCUITS;

EID: 33646928098     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.281     Document Type: Conference Paper

References (10)

1. M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," TAU 97, Austin, TX, December 1997
2. J.J Liou, K.T.Cheng, S.Kundu, A.Krstic, "Fast Statistical Timing Analysis By Probabilistic Event Propagation", DAC 2001
3. A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula, "Computation and Refinement of Statistical Bounds on Circuit Delay," DAC 2003.
4. A. Devgan, C. Kashyap, "Block-based Static Timing Analysis with Uncertainty," ICCAD 2003, pp.607-614
5. H. Chang, S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-like Traversal," ICCAD'03.
6. H. Hashimoto, H. Onodera. "Increase in delay uncertainty by performance optimization", ISCAS 2001, pp. 379-382.
7. X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway. "Uncertainty-aware circuit optimization", DAC 2002.
8. E.T.A.F. Jacobs, M.R.C.M Berkelaar. "Gate sizing using a statistical delay model", DATE 2000, pp. 283-289.
9. S. Raj, S. Vrudhula, J. Wang. "A methodology to improve timing yield in the presence of process variations", DAC 2004.
10. F. Brglez, H.Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits", Proc. ISCAS, 1985, pp.695-698.