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Volumn , Issue , 2005, Pages 284-290

Parametric yield analysis and constrained-based supply voltage optimization

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY CONSTRAINT; INDUSTRY PROCESS; MATHEMATICAL FRAMEWORKS; PARAMETRIC YIELD; POWER CONSTRAINTS; PROCESS VARIATION; YIELD ESTIMATION; YIELD MAXIMIZATION;

EID: 84886705903     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.90     Document Type: Conference Paper
Times cited : (18)

References (12)
  • 1
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  • 2
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    • S. R. Nassif, "Modeling and Analysis of Manufacturing Variations," CICC, pp. 223-228, 2001.
    • (2001) CICC , pp. 223-228
    • Nassif, S.R.1
  • 3
    • 84886694399 scopus 로고    scopus 로고
    • http://developer.intel.com/design/mobile/datashts
  • 4
    • 84949480508 scopus 로고    scopus 로고
    • Design sensitivities to variability: Extrapolation and assessments in nanometer vlsi
    • Y. Cao, et.al, "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI," ASIC-SOC, pp. 411-415, 2002.
    • (2002) ASIC-SOC , pp. 411-415
    • Cao, Y.1
  • 5
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variation and impact on circuit and micro-architecture
    • S. Borkar, et.al, "Parameter variation and impact on circuit and micro-architecture," DAC, pp. 338-342, 2003.
    • (2003) DAC , pp. 338-342
    • Borkar, S.1
  • 6
    • 0036923996 scopus 로고    scopus 로고
    • A high-performance 90nm SOI technology with 0.99 mm 6T-SRAM cell
    • M. Khare, et.al, "A high-performance 90nm SOI technology with 0.99 mm 6T-SRAM cell," IEDM, pp. 407-410, 2002.
    • (2002) IEDM , pp. 407-410
    • Khare, M.1
  • 8
    • 0036954781 scopus 로고    scopus 로고
    • Modeling and analysis of leakage power considering within-die process variations
    • 02
    • A. Srivastava, et.al, "Modeling and Analysis of Leakage Power Considering Within-Die Process Variations," ISLPED, pp. 64-67, 02.
    • ISLPED , pp. 64-67
    • Srivastava, A.1
  • 9
    • 0025415048 scopus 로고
    • Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas
    • T. Sakurai, et.al, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," Journal of Solid-State Circuits, vol. 25, pp. 584-594, 1990.
    • (1990) Journal of Solid-State Circuits , vol.25 , pp. 584-594
    • Sakurai, T.1
  • 10
    • 0027256982 scopus 로고
    • Trading speed for low power by choice of supply and threshold voltage
    • D. Liu and C. Svensson, "Trading Speed for low power by choice of supply and threshold voltage," JSSC, vol. 28, pp. 10-17, 1993.
    • (1993) JSSC , vol.28 , pp. 10-17
    • Liu, D.1    Svensson, C.2
  • 11
    • 0142039803 scopus 로고    scopus 로고
    • Delay defect characteristics and testing strategies
    • S. Kee, S. Mitra and P. Ryan, "Delay defect characteristics and testing strategies," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 8-16, 2003.
    • (2003) IEEE Design and Test of Computers , vol.20 , Issue.5 , pp. 8-16
    • Kee, S.1    Mitra, S.2    Ryan, P.3
  • 12
    • 0142135003 scopus 로고    scopus 로고
    • Speed binning with path delay test in 150-nm technology
    • B. Croy, R. Kapur and B. Underwood, "Speed binning with path delay test in 150-nm technology," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 41-45, 2003.
    • (2003) IEEE Design and Test of Computers , vol.20 , Issue.5 , pp. 41-45
    • Croy, B.1    Kapur, R.2    Underwood, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.