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Volumn , Issue , 2004, Pages 664-669

Static timing analysis using backward signal propagation

Author keywords

Algorithms; Performance; Reliability

Indexed keywords

ALGORITHMS; BENCHMARKING; ERROR CORRECTION; MATHEMATICAL MODELS; OPTIMIZATION; RELIABILITY; SIGNAL PROCESSING; STATISTICAL METHODS;

EID: 4444259541     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996747     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 4
    • 0027849390 scopus 로고
    • Computation of floating mode delay in combinational circuit: Theory and algorithms
    • Dec.
    • S.Devadas, K.Keutzer, S.Malik, "Computation of Floating Mode Delay in Combinational Circuit: Theory and Algorithms", IEEE Trans. on Computer Aided Design, Vol. 12, No. 12, pp. 1913-1923, Dec. 1993.
    • (1993) IEEE Trans. on Computer Aided Design , vol.12 , Issue.12 , pp. 1913-1923
    • Devadas, S.1    Keutzer, K.2    Malik, S.3
  • 8
    • 0030403625 scopus 로고    scopus 로고
    • Noise in deep submicron digital design
    • K. Shepard, V. Narayanan, "Noise in Deep Submicron Digital Design," Proc. ICCAD 1996, pp. 524-531.
    • Proc. ICCAD 1996 , pp. 524-531
    • Shepard, K.1    Narayanan, V.2
  • 9
    • 0033885244 scopus 로고    scopus 로고
    • Capturing the effect of crosstalk on delay
    • January
    • S. Sapatnekar, "Capturing the Effect of Crosstalk on Delay," Proc. VLSI Design 2000, pp. 364-369, January 2000.
    • (2000) Proc. VLSI Design 2000 , pp. 364-369
    • Sapatnekar, S.1
  • 10
    • 0034846652 scopus 로고    scopus 로고
    • Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
    • G. Bai, S. Bobba, I. Hajj, "Static timing analysis including power supply noise effect on propagation delay in VLSI circuits," Proc. DAC, 2001, pp. 295 -300.
    • (2001) Proc. DAC , pp. 295-300
    • Bai, G.1    Bobba, S.2    Hajj, I.3
  • 12
    • 0033351695 scopus 로고    scopus 로고
    • Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
    • Chandu Visweswariah, Andrew R.Conn, "Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation", ICCAD, 1999, pp.244-251.
    • (1999) ICCAD , pp. 244-251
    • Visweswariah, C.1    Conn, A.R.2
  • 14
    • 84862411130 scopus 로고    scopus 로고
    • http://www.cbl.ncsu.edu.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.