Sub-90nm technologies--challenges and opportunities for CAD

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 203-206

  Karnik, Tanay ^a   Borkar, Shekhar ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC DESIGN AUTOMATION; SUBTHRESHOLD LEAKAGE;

AUTOMATION; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LEAKAGE CURRENTS; PROBABILITY; STATISTICAL METHODS; THRESHOLD VOLTAGE;

MICROPROCESSOR CHIPS;

EID: 0036911849     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774602     Document Type: Conference Paper

References (10)

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4. Tschanz, J., et al., "Design optimizations of a high performance microprocessor using combinations of dual-Vt allocation and transistor sizing", VLSI Circuits Symposium 2001, pp. 218-219.
5. Pant, P., et al., Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits. TVLSI, Vol. 9, No. 2, 4, 2001, pp. 390-394.
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7. Anis, M., et al., Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. DAC 2002, pp. 480-485
8. Kuroda, T., et al., Low-power CMOS digital design with dual embedded adaptive power supplies. JSSC, Vol. 35, Issue 4, April 2000, pp. 652-655.
9. Krishnamurthy, R., et al., High-performance and low-power challenges for sub-70nm microprocessor circuits. CICC 2002, pp. 125-128.
10. Keshavarzi A., et al., Forward body bias for uPs in 130nm technology generation and beyond. VLSI Circuits Symp. 2002 pp. 125-128.