Engineering wafers for the nanotechnology era

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 29-38

  Mazuré, Carlos ^a   Auberton Hervé, André Jacques ^a  

^a PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; PRINTED CIRCUIT DESIGN; SEMICONDUCTOR DEVICES; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES;

CURRENT DRIVES; GERMANIUM ON INSULATOR; IC PERFORMANCE; PARASITIC ELEMENTS;

NANOTECHNOLOGY;

EID: 33749165701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541554     Document Type: Conference Paper

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