Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

IEEE Transactions on Electron Devices

Volumn 53, Issue 1, 2006, Pages 135-144

  Yu, Sunil ^a,b,c   Petranovic, Dusan M ^c,d   Krishnan, Shoba ^c   Lee, Kwyro ^a,b   Yang, Cary Y ^c  

^a Korea Advanced Institute of Science and Technology ^*

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c SANTA CLARA UNIVERSITY   (United States)

^d MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Electromagnetic coupling; Inductance; Integrated circuit interconnections, modeling

Indexed keywords

ALGORITHMS; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTROMAGNETIC COUPLING; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; LUMPED PARAMETER NETWORKS; MATHEMATICAL MODELS;

CURRENT DISTRIBUTION; INTEGRATED CIRCUIT INTERCONNECTIONS; MULTICONDUCTORS;

MICROPROCESSOR CHIPS;

EID: 33748312331     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.860655     Document Type: Article

References (37)

1. Y. I. Ismail, "On-chip inductance cons and pros," IEEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 10, no. 6, pp. 685-694, Dec. 2002.
2. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 5, pp. 490-504, May 2001.
3. S. S. Wong, P. Yue, R. Chang, S.-Y. Kim, B. Kleveland, and F. O'Mahony, "On-chip interconnect inductance - Friend or foe," in Proc. ISQED, Mar. 2003, pp. 389-394.
4. Y. Massoud, S. Mayors, J. Kawa, T. Bustami, D. MacMillen, and J. White, "Managing on-chip inductive effects," IEEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 10, no. 6, pp. 789-798, Dec. 2002.
5. S. V. Morton, "On-chip inductance issues in multiconductor systems," in Proc. DAC, Jun. 1999, pp. 921-926.
6. A. E. Ruehli, "Inductance calculation in a complex integrated circuit environment," IBM J. Res. Develop., vol. 16, pp. 470-481, 1972.
7. K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao, "Inductance 101: Analysis and design issues," in Proc. DAC, Jun. 2001, pp. 329-334.
8. M. W. Beattie and L. T. Pileggi, "On-chip induction modeling: Basics and advanced method," EEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 10, no. 6, pp. 712-729, Dec. 2002.
9. G. V. Kopcsay, B. Krauter, D. Widiger, A. Deutsch, B. J. Rubin, and H. H. Smith, "A comprehensive 2-D inductance modeling approach for VLSI interconnects: Frequency-dependent extraction and compact circuit model synthesis," EEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 10, no. 6, Dec. 2002.
10. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," IEEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 13, no. 1, pp. 158-162, Jan. 2005.
11. N. Arora, L. Song, and V. Chang, "Modeling and characterization of on-chip inductance for sub 100 nm Cu CMOS process," presented at the Proc. Compact Modeling Symp., Santa Clara, May 7, 2004.
12. B. Krauter and S. Mehrtra, "Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis," in Proc. DAC, 1998, pp. 303-308.
13. S.-P. Sim, S. Krishnan, D. M. Petranovic, N. D. Arora, K. Lee, and C. Y. Yang, "A unified RLC model for high-speed on-chip interconnects," IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1501-1510, Jun. 2003.
14. X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King, and C. Hu, "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 457-463, Mar. 2003.
15. B. Kleveland, X. Qi, L. Madden, T. Furusawa, R. W. Dutton, M. A. Horowitz, and S. S. Wong, "High-frequency characterization of on-chip digital interconnects," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 716-725, Jun. 2002.
16. K. L. Shepard and Z. Tian, "Return-limited inductances: A practical approach to on-chip inductance extraction," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 4, pp. 425-436, Apr. 2000.
17. D. Goren, M. Zelikson, T. C. Galambos, R. Gordin, B. Livshitz, A. Amir, A. Sherman, and I. A. Wagner, "An interconnect-aware design methodology for analog and mixed signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach," in Proc. DATE, Mar. 2002, pp. 804-811.
18. A. Deutsh, H. H. Smith, C. W. Surovic, G. V. Kopcsay, D. A. Webber, P. W. Coteus, G. A. Katopis, W. D. Becker, A. H. Dansky, G. A. Sai-Halasz, and P. J. Restle, "Freqeuncy-dependent crosstalk simulation for on-chip interconnects," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 292-308, Aug. 1999.
19. I. M. Elfadel, A. Deutsch, H. H. Smith, B. J. Rubin, and G. V. Kopcsay, "A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis," IEEE Trans. Adv. Packag., vol. 27, no. 1, pp. 71-78, Feb. 2004.
20. S. V. Morton, "On-chip signaling," in Proc. IEEE ISSCC, Feb. 2002, pp. 554-557.
21. S. Yu, D. M. Petranovic, S. Krishnan, K. Lee, and C. Y. Yang, "Resistance matrix in crosstalk modeling for multiconductor systems," in Proc. ISQED, Mar. 2004, pp. 122-125.
22. M. H. Chowdhury, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, "Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance," in Proc. IEEE ISCAS, vol. 4, May 2002, pp. 26-29.
23. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
24. J. A. Davis and J. D. Meindle, "Compact distributed RLC interconnect models - Part II: Coupled line transient expression and peak crosstalk in multilevel network," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078-2087, Nov. 2000.
25. Y. Eo, S. Shin, W. R. Eisenstadt, and J. Shim, "Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 12, pp. 1489-1497, Dec. 2002.
26. J. E. Bracken, "Mutual Resistance in Spicelink," Ansoft Corporation, Pittsburgh, PA, 2000.
27. B. Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages. Englewood Cliffs, NJ: Prentice-Hall, 2001.
28. F. W. Grover, Inductance Calculations: Working Formulas and Tables. New York: Dover, 1946.
29. A. Budak, Passive and Active Network Analysis andSynthesis. Boston, MA: Houghton Mifflin, 1974.
30. Maxwell Q2D/Q3D Parameter Extractor User's Guide, Ansoft Corporation, Pittsburgh, PA, 2003.
31. T. Lin, M. W. Beattie, and L. T. Pileggi, "On the efficacy of simplified 2-D on-chip inductance models," in Proc. DAC, Jun. 2002, pp. 757-762.
32. C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, "Design of CMOS for 60 GHz applications," in Proc. IEEE ISSCC, Feb. 2004, pp. 440-448.
33. S.-P. Sim, K. Lee, and C. Y. Yang, "High-frequency on-chip inductance model," IEEE Electron Device Lett., vol. 23, no. 12, pp. 740-742, Dec. 2002.
34. Y.-C. Lu, M. Celik, T. Young, and L. T. Pilleggi, "Min/max on-chip inductance models and delay metrics," in Proc. DAC, Jun. 2001, pp. 341-346.
35. M. Kamon, M. J. Tsuk, and J. K. White, "FASTHENRY: A multipile-accelerated 3-D inductance extraction program," IEEE Trans. Microw.Theory Tech., vol. 42, no. 9, pp. 1750-1758, Sep. 1994.
36. W. R. Eisenstadt and Y. Eo, "S-Parameter-based IC interconnect transmission line characterization," IEEE Trans Compon., Hybrids, Manufact. Technol., vol. 15, no. 4, pp. 483-490, Aug. 1992.
37. J. C. Rautio, "Techniques for correcting scattering parameter data of an imperfectly terminated multiport when measured with a two-port network analyzer," IEEE Trans. Microw. Theory Tech., no. 5, pp. 407-412, May 1983.