Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 303-308

  Krauter, Byron ^a   Mehrotra, Sharad ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EXTRACTION; INDUCTANCE; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; TIMING CIRCUITS;

FREQUENCY DEPENDENT; FREQUENCY DEPENDENT INDUCTANCE; FREQUENCY INDEPENDENT; LOW FREQUENCY RESISTANCES; LUMPED-ELEMENT CIRCUITS; ON CHIP INTERCONNECT; PROXIMITY AND SKIN EFFECTS; RESISTANCE EXTRACTION;

TIMING CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

ON-CHIP INTERCONNECT TIMING ANALYSIS;

EID: 0031622874     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277133     Document Type: Conference Paper

References (7)

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4. D.P.Neikirk, Private communication.
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7. H.A.Wheeler, "Formulas for the Skin-Effect, '' Proceedings of the Institute of Radio Engineers, vol. 30, pp. 412-424, Sept. 1942.