Min/max on-chip inductance models and delay metrics

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 341-346

  Lu, Y C ^a   Celik, M ^a   Young, T ^a   Pileggi, L T ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Delay; Inductance; On chip interconnect modeling; Physical design; RLC tree

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; INDUCTANCE; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; OPTIMIZATION;

ON-CHIP INDUCTANCE MODELS;

CHIP SCALE PACKAGES;

EID: 0034853859     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378506     Document Type: Conference Paper

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