Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages 197-200

  Chowdhury, Masud H ^a   Ismail, Yehea I ^a   Kashyap, Chandramouli V ^b   Krauter, Byron L ^b  

^a Northwestern University   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INDUCTANCE; INTERCONNECTION NETWORKS; TREES (MATHEMATICS);

ELMORE DELAY; OVERSHOOTS; PROPAGATION DELAY;

VLSI CIRCUITS;

EID: 0036292725     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010423     Document Type: Article

References (19)

1. The effects of interconnections on high-speed logic circuits
2. Performance optimization of VLSI interconnect
3. Effects of inductance on propagation delay and repeater insertion in VLSI circuits
4. Figures of merit to characterize the importance of on-chip inductance
5. Equivalent elmore delay for RLC trees
6. Effects of scaling of interconnects on the time delay of VLSI circuits
7. On-chip wiring design challenges for gigahertz operation
8. On-chip inductance issues in multiconductor systems
9. Inductance 101: Analysis and design issues
10. The importance of inductance and inductive coupling for on-chip wiring
11. The transient response of damped linear networks
12. Where are transmission-line effects important for on-chip interconnections?
13. Improved delay prediction for on-chip buses
14. Full-wave PEEC time-domain method for the modeling of interconnect
15. A realizable driving point model for on-chip interconnect with inductance
16. Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis