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Volumn 13, Issue 1, 2005, Pages 158-162

Impact of on-chip interconnect frequency-dependent R(f) L(f) on digital and RF design

Author keywords

Delay; Frequency dependence; Inductance; Noise; Over shoot; Quality factor; Resistance; Slew rate

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ELECTRIC RESISTANCE; INDUCTANCE; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE;

EID: 13144278327     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.840399     Document Type: Article
Times cited : (12)

References (16)
  • 2
    • 0001032562 scopus 로고
    • Inductance calculations in a complex integrated circuit environment
    • Sept.
    • A. E. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM J. Res. Develop., pp. 470-481, Sept. 1972.
    • (1972) IBM J. Res. Develop. , pp. 470-481
    • Ruehli, A.E.1
  • 3
    • 0037348311 scopus 로고    scopus 로고
    • Frequency-independent equivalent circuit model for on-chip spiral inductors
    • Mar.
    • Y. Cao et al., "Frequency-independent equivalent circuit model for on-chip spiral inductors," IEEE J. Solid-State Circuits, vol. 38, pp. 419-426, Mar. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , pp. 419-426
    • Cao, Y.1
  • 4
    • 0029719729 scopus 로고    scopus 로고
    • Compact equivalent circuit model for the skin effect
    • June
    • S. Kim and D. P. Neikirk, "Compact equivalent circuit model for the skin effect," in Proc. Int. Microwave Symp., June 1996, pp. 1815-1818.
    • (1996) Proc. Int. Microwave Symp. , pp. 1815-1818
    • Kim, S.1    Neikirk, D.P.2
  • 5
    • 0003394064 scopus 로고    scopus 로고
    • Englewood Cliffs: Prentice-Hall, ch. NJ
    • B. Young, Digital Signal Integrity. Englewood Cliffs: Prentice-Hall, 2001, ch. NJ.
    • (2001) Digital Signal Integrity
    • Young, B.1
  • 6
    • 0033712809 scopus 로고    scopus 로고
    • On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation
    • May
    • X. Qi et al., "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation," in IEEE Custom Integrated Circuits Conf., May 2000, pp. 487-490.
    • (2000) IEEE Custom Integrated Circuits Conf. , pp. 487-490
    • Qi, X.1
  • 8
    • 0031622874 scopus 로고    scopus 로고
    • Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
    • June
    • B. Krauter and S. Mehrotra, "Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis," in IEEE Design Automation Conf., June 1998, pp. 303-308.
    • (1998) IEEE Design Automation Conf. , pp. 303-308
    • Krauter, B.1    Mehrotra, S.2
  • 11
    • 0034841994 scopus 로고    scopus 로고
    • Modeling and analysis of differential signaling for minimizing inductive cross-talk
    • June
    • Y. Massoud, J. Kawa, D. MacMillen, and J. White, "Modeling and analysis of differential signaling for minimizing inductive cross-talk," in IEEE Design Automation Conf., June 2001, pp. 804-809.
    • (2001) IEEE Design Automation Conf. , pp. 804-809
    • Massoud, Y.1    Kawa, J.2    MacMillen, D.3    White, J.4
  • 12
    • 0034453548 scopus 로고    scopus 로고
    • RLC signal integrity analysis of high-speed global interconnects
    • Dec.
    • X. Huang et al., "RLC signal integrity analysis of high-speed global interconnects," in IEEE Int. Electron Devices Meeting, Dec. 2000, pp. 731-734.
    • (2000) IEEE Int. Electron Devices Meeting , pp. 731-734
    • Huang, X.1
  • 14
    • 0034428197 scopus 로고    scopus 로고
    • An on-chip voltage regulator using switched decoupling capacitors
    • Feb.
    • M. Ang, R. Salem, and A. Taylor, "An on-chip voltage regulator using switched decoupling capacitors," in IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp. 438-439.
    • (2000) IEEE Int. Solid-state Circuits Conf. , pp. 438-439
    • Ang, M.1    Salem, R.2    Taylor, A.3
  • 15
    • 0031103498 scopus 로고    scopus 로고
    • The modeling, characterization, and design of monolithic inductors for silicon RF IC's
    • Mar.
    • J. R. Long and M. A. Copeland, "The modeling, characterization, and design of monolithic inductors for silicon RF IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 357-369, Mar. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 357-369
    • Long, J.R.1    Copeland, M.A.2
  • 16
    • 0035215349 scopus 로고    scopus 로고
    • CAD solutions and out-standing challenges for mixed-signal and RF IC design
    • Nov.
    • D. Leenaerts, G. Gielen, and R. A. Ruterbar, "CAD solutions and out-standing challenges for mixed-signal and RF IC design," in IEEE Int. Conf. Computer Aided Design, Nov. 2001, pp. 270-277.
    • (2001) IEEE Int. Conf. Computer Aided Design , pp. 270-277
    • Leenaerts, D.1    Gielen, G.2    Ruterbar, R.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.