Mosfet's negative transconductance at room temperature

IEEE Transactions on Electron Devices

Volumn 46, Issue 6, 1999, Pages 11891195-

  Versari, Roberto ^a,b   Riccö, Bruno ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Effective mobility; MOSFET; Negative transconductance; Room temperature

Indexed keywords

EID: 33747154085     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (30)

1. F. T. Fang and W. E. Howard, "Negative field effect mobility on (100) Si surfaces," Phys. Rev. Lett., vol. 16, p. 797, 1966.
2. F. T. Fang and A. B. Fowler, "Transport properties of electrons in inverted silicon surfaces," Phys. Rev., vol. 169, p. 619, 1968.
3. T. C. Ong, P. K. Ko, and C. Hu, "50Å gateoxide MOSFET's at 77 K," IEEE Trans. Electron Devices, vol. ED34, p. 2129, Oct. 1987.
4. J. I. Lee, M. B. Lee, and K. N. Kang, "Simple extraction method for mobility parameters in SiMOSFET's at 77 K," Electron. Lett., vol. 26, p. 852, 1990.
5. T. Hori, "Inversion layer mobility under high normal field in nitridedoxide MOSFET's," IEEE Trans. Electron Devices, vol. 37, p. 2058, Sept. 1990.
6. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part IEffects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, p. 2357, Dec. 1994.
7. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part IIEffects of surface orientation," IEEE Trans. Electron Devices, vol. 41, p. 2363, Dec. 1994.
8. R. Versari and B. Riccö, "Scaling of maximum capacitance of MOSFET with ultrathin oxide," Electron. Lett., vol. 34, p. 2175, 1998.
9. K. S. Krish, J. D. Bude, and L. Manchanda, "Gate capacitance attenuation in MOS devices with thin gate dielectrics," IEEE Electron Device Lett., vol. 17, p. 521, Nov. 1996.
10. F. Rana, S. Tiwari, and D. A. Buchanan, "Selfconsistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, p. 1104, 1996.
11. A. Pacelli, "Selfconsistent solution of the Schrödinger equation in semiconductor devices by implicit iteration," IEEE Trans. Electron Devices, vol. 44, p. 1169, July 1997.
12. C. L. Huang, J. V. Faricelli, and N. D. Arora, "A new technique for measuring MOSFET inversion layer mobility," IEEE Trans. Electron Devices, vol. 40, p. 1134, June 1993.
13. M. Ishizaka, T. lizuka, S. Ohi, M. Fukuma, and H. Mikoshiba, "Advanced electron mobility model of MOS inversion layer considering 2Ddegenerated electron gas physics," IEDM Tech. Dig., 1990, p. 763.
14. C. Jungemann, A. Emunds, and W. L. Engl, "Simulation of linear and nonlinear electron transport in homogeneous silicon inversion layers," Solid State Electron., vol. 36, p. 1529, 1993.
15. x substrates," Appl. Phys. Lett., vol. 63, p. 186, 1993.
16. 2 interface," Phys. Rev. B, vol. 32, p. 8171, 1985.
17. D. Vasileska and D. K. Ferry, "Scaled silicon MOSFET's: Universal mobility behavior," IEEE Trans. Electron Devices, vol. 44, p. 577, Apr. 1997.
18. F. Gàmiz, J. A. L. Villanueva, J. A. J. Tejada, I. Melchor, and A. Palma, "A comprehensive model for Coulomb scattering in inversion layers," J. Appl. Phys., vol. 75, p. 924, 1994.
19. M. V. Fischetti and S. E. Laux, "Monte Carlo study of electron transport in silicon inversion layers," Phys. Rev. B, vol. 48, p. 2244, 1993.
20. G. L. Chindalore, J. B. McKeon, S. Mudanai, S. A. Hareland, W. K. Shih, C. Wang, Al F. Tasch Jr., and C. M. Maziar, "An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers," IEEE Trans. Electron Devices, vol. 45, p. 502, Feb. 1998.
21. J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Trans. Electron Devices, vol. 43, p. 1981, Nov. 1996.
22. L. Perron, A. L. Lacaita, S. Guzzetti, and R. Bez, "Impact of fast interface states on effective mobility of heavily doped MOSFET's," Proc. ESSDERC'96, p. 833.
23. L. Perron, A. L. Lacaita, A. Pacelli, and R. Bez, "Electron mobility in ULSI MOSFET's: Effect of interface traps and oxide nitridation," IEEE Electron Device Lett., vol. 18, p. 235, May 1997.
24. B. J. Sheu, C. Hu, P. K. Ko, and F. C. Hsu, "Source and drain series resistance of LDD MOSFET s," IEEE Electron Device Lett., vol. EDL5, p. 365, Sept. 1984.
25. J. A. L. Villanueva, P. C. Casinello, J. Banqueri, F. Gâmiz, and S. Rodriguez, "Effects of the inversion layer centroid on MOSFET behavior," IEEE Trans. Electron Devices, vol. 44, p. 1915, Nov. 1997.
26. T. Skotnicki, "Advanced architectures for 0.180.12 μm CMOS generations," in Proc. ESSDERC'96. p. 505.
27. O. Faynot, S. Cristoloveanu, P. McLarty, C. Raynaud, and J. Gautier, "A new parameter extraction method for ultrathin oxide SOI MOSFET's," Proc. IEEE Int. SOI Conf., 1994, p. 17.
28. S. Villa, A. L. Lacaita, L. M. Perron, and R. Bez, "A physicallybased model of the effective mobility in heavilydoped nMOSFET's," IEEE Trans. Electron Devices, vol. 45, p. 110, Jan. 1998.
29. F. Gàmiz, J. L. Villanueva, J. Banqueri, J. Carceller, and P. Cartujo, "A comparison of models for phonon scattering in silicon inversion layers," J. Appl. Phys., vol. 77, p. 4128, 1995.
30. J. Koga, S. Takagi, and A. Toriumi, "Observation of oxide thickness dependent interface roughness in Si MOS structure," Jpn. J. Appl. Phys., vol. 35, p. 1440, 1996.