Source-and-Drain Series Resistance of LDD MOSFET’s

IEEE Electron Device Letters

Volumn 5, Issue 9, 1984, Pages 365-367

  Sheu, B J ^a   Hu, C ^a   Ko, P K ^a   Hsu, F C ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS - APPLICATIONS;

APPARENT CHANNEL LENGTH; GATE BIAS; LIGHTLY-DOPED DRAIN-SOURCE (LDD) MOSFET; SOURCE-AND-DRAIN SERIES RESISTANCE;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0021489601     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1984.25948     Document Type: Article

References (5)

1. S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, “Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 424-432, Aug. 1980.
2. P. I. Suciu and R. L. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1846-1848, Sept. 1980.
3. J. G. J. Chen, P. Chang, R. F. Motta, and N. Godinho, “A new method to determine MOSFET channel length,” IEEE Electron Device Lett., vol. EDL-1, pp. 170-173, Sept. 1980.
4. C. Duvvury, D. Baglee, M. Duane, A. Myslop, M. Smayling, and M. Maekawa, “An analytical method for determining intrinsic drain source resistance of lightly doped drain (LDD) devices,” Solid State Electron., vol. 27, no. 1, pp. 89-96, 1984.
5. P. Antognetti, C. Lombardi, and D. Antoniadis, “Use of process and 2-D MOS simulation in the study of doping profile influence on S/D resistance in short channel MOSFET's,” in IEDM Tech. Dig., 1981, pp. 574-577.