Scaling of maximum capacitance of MOSFET with ultra-thin oxide

Electronics Letters

Volumn 34, Issue 22, 1998, Pages 2175-2176

  Versari, R ^a   Ricco B ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); OXIDES; SEMICONDUCTOR DOPING; SUBSTRATES;

GATE OXIDE; SUBSTRATE DOPING;

MOSFET DEVICES;

EID: 0032179720     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981471     Document Type: Article

References (6)

1. TAKAGI, S., and TORIUMI, A.: 'Quantitative understanding of inversion-layer capacitance in Si MOSFETs', IEEE Trans., 1995, ED-42, pp. 2125-2130
2. VASILESKA, D., SCHRODER, D.K., and FERRY, D.K.: 'Scaled silicon MOSFETs: Degradation of the total gate capacitance', IEEE Trans., 1997, ED-44, pp. 584-587
3. KRISH, K.S., BUDE, J.D., and NIANCHANDA, L.: 'Gate capacitance attenuation in MOS devices with thin gate dielectrics', IEEE Electron Dev. Lett., 1996, 17, pp. 521-524
4. RICCÒ, B., VERSARI, R., and ESSENI, D.: 'Characterization of polysilicon-gate depletion in MOS structures', IEEE Electron Dev. Lett., 1996, 17, pp. 103-105
5. PACELLI, A.: 'Self-consistent solution of the Schrödinger equation in semiconductor devices by implicit iteration', IEEE Trans., 1997, ED-44, pp. 1169-1171
6. TAUR, Y., BUCHANAN, D.A., CHEN, W., FRANK, D.J., ISMAIL, K.E., LO, S., SAI-HALASZ, G.A., VISWANATHAN, R.G., WANN, H.C., WIND, S.J., and WONG, H.: 'CMOS scaling into the nanometer regime', Proc. IEEE, 1997, 85, pp. 486-504