Reducing the complexity of the register file in dynamic superscalar processors

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 2001, Pages 237-248

  Balasubraamonian, Rajeev ^a   Dwarkadas, Sandhya ^a   Albonesi, David H ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SHIFT REGISTERS;

INSTRUCTION-LEVEL PARALLELISM (ILP); SUPERSCALAR PROCESSORS;

PROGRAM PROCESSORS;

EID: 0035696763     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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