Enhancing Memory Level Parallelism via Recovery-Free Value Prediction

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2003, Pages 326-335

  Zhou, Huiyang ^a   Conte, Thomas M ^a  

^a North Carolina State University   (United States)

Author keywords

Memory disambiguation; Memory level parallelism; Prefetching; Recovery free value prediction

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; SENSITIVITY ANALYSIS;

MEMORY DISAMBIGUATION; MEMORY LEVEL PARALLELISM; PREFETCHING; RECOVERY-FREE VALUE PREDICTION;

DATA STORAGE EQUIPMENT;

EID: 1142293060     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/782814.782859     Document Type: Conference Paper

References (30)

1. th International Symposium on Microarchitecture (MICRO-26), 1993.
2. th International Symposium on Computer Architecture (ISCA-26), 1999.
3. D. Burger and T. Austin, "The SimpleScalar tool set, v2.0", Computer Architecture News (ACM SIGARCH newsletter), vol. 25, June 1997.
4. B. Calder and G. Reinman, "A comparative survey of load speculation architecures", Journal of Instruction-Level Parallelism, 2000.
5. M. Carlisle, "Olden: parallelizing programs with dynamic data structures on distributed-memory machines", Ph.D. thesis, Princeton University Computer Science Department, 1996
6. th International Symposium on Computer Architecture (ISCA-28), 2001
7. th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002.
8. J. Dundas, and T. Mudge, "Improving data cache performance by pre-executing instructions under a cache miss", Proceeding of the 1997 International Conference on Supercomputing, 1997.
9. F. Gabbay and A. Mendelson, "Speculative execution based on value prediction," EE Department Tech Report 1080, Tachnion - Israel Institute of Technology, Nov. 1996.
10. J. Gonzalez and A. Gonzalez, "Speculative execution via address prediction and data prefetching", Proceeding of the 1997 International Conference on Supercomputing, 1997.
11. J. Henning, "SPEC2000: measuring CPU performance in the new millennium", IEEE Computer, July 2000.
12. D. Joseph and D. Grunwald, "Prefetching using Markov Predictors", IEEE Transactions on Computers. Vol. 48, Feb 1999.
13. T. Karkhanis and J. Smith, "A Day in the Life of a Cache Miss", Proceeding of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), 2002.
14. th International Symposium on Computer Architecture (ISCA-29), 2002.
15. S. Lee and P. Yew, "On some implementation issues for value prediction on wide ILP processors", Proceeding of the International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000.
16. th International Symposium on Microarchitecture (MICRO-29), 1996.
17. th International Conference on Architectural Support for Programming Language and Operation Systems (ASPLOS-7), Oct, 1996.
18. th International Symposium on Computer Architecture (ISCA-28), 2001.
19. th International Symposium on High Performance Computer Architecture (HPCA-9), 2003.
20. E. Rotenberg, S. Bennett, and J. E. Smith. "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching", Proceeding of the 29th International Symposium on Microarchitecture (MICRO-29), 1996.
21. th International Symposium on High Performance Computer Architecture (HPCA-7), 2001.
22. th International Symposium on Microarchitecture (MCRO-30), Nov. 1997.
23. th International Symposium on Computer Architecture (ISCA-29), 2002.
24. th International Symposium on Microarchitecture (MICRO-30), Nov. 1997.
25. th International Symposium on High Performance Computer Architecture (HPCA-8), 2002.
26. Y. Wu, "Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching", Proceeding of the ACM 2002 Conference on Programming Language Design and Implementation (PLDI-2002), 2002.
27. K. C. Yeager, "The MIPS R10000 superscalar microprocessor", IEEE Micro, 1996.
28. th Int'1 Symp. on Computer Architecture (ISCA-30), 2003.
29. H. Zhou and T. Conte, "Performance modeling of memory latency hiding techniques", Technical Report, ECE Department, N. C. State university, Dec. 2002
30. th International Symposium on Computer Architecture (ISCA-28), 2001.