Instruction level parallelism through microthreading - A scalable approach to chip multiprocessors

Computer Journal

Volumn 49, Issue 2, 2006, Pages 211-233

  Bousias, Kostas ^a   Hasasneh, Nabil ^b   Jesshope, Chris ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

^b UNIVERSITY OF HULL   (United Kingdom)

Author keywords

CMP; Code fragments; Concurrency; Microthreads

Indexed keywords

COMPUTATIONAL COMPLEXITY; CONCURRENCY CONTROL; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; SYNCHRONIZATION;

CODE FRAGMENTS; INSTRUCTION LEVEL PARALLELISM (ILP); MICROTHREADS;

MICROPROCESSOR CHIPS;

EID: 33644893333     PISSN: 00104620     EISSN: 14602067     Source Type: Journal    
DOI: 10.1093/comjnl/bxh157     Document Type: Article

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