Reducing register ports for higher speed and lower energy

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 171-182

  Park, Il ^a   Powell, Michael D ^a   Vijaykumar, T N ^a  

^a Purdue University   (United States)

Author keywords

Bandwidth; Banking; Delay; Design engineering; Pipelines; Power engineering and energy; Proposals; Registers; Tagging; Timing

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; PIPELINES;

BANKING; DELAY; DESIGN ENGINEERING; POWER ENGINEERING AND ENERGIES; PROPOSALS; REGISTERS; TAGGING; TIMING;

PIPELINE PROCESSING SYSTEMS;

EID: 41349090027     PISSN: 10724451     EISSN: None     Source Type: Journal    
DOI: 10.1109/MICRO.2002.1176248     Document Type: Article

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