Instruction wake-up in wide issue superscalars

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2150, Issue , 2001, Pages 418-427

  Önder, Soner ^a   Gupta, Rajiv ^b  

^a MICHIGAN TECHNOLOGICAL UNIVERSITY   (United States)

^b UNIVERSITY OF ARIZONA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL PROCESSING SYSTEMS;

EFFECTIVE APPROACHES; INSTRUCTION WINDOWS; LARGE INSTRUCTION WINDOW; MICRO ARCHITECTURES; SUPERSCALAR PROCESSOR; WAKE UP;

WAKES;

EID: 65349143924     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44681-8_61     Document Type: Conference Paper

References (5)

1. S. Önder and R. Gupta. Scalable Superscalar Processing. Ph. D. Thesis, Univ. of Pttsburgh, July 1999.
2. S. Önder and R. Gupta. Superscalar execution with dynamic data forwarding. In International Conference on Parallel Architectures and Compilation Techniques, pages 130–135, October 1998.
3. S. Önder and R. Gupta. Dynamic memory disambiguation in the presence of outof-order store issuing. To appear in the 32nd Annual IEEE-ACM International Symposium on Microarchitecture, November 1999.
4. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th International Conference on Computer Architecture, pages 206–218, June 1997.
5. S. Vajapeyam and T. Mitra. Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences. In Proceedings of the 24th International Conference on Computer Architecture, pages 1–12, June 1997.