Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2003, Pages 172-182

  Kim, Nam Sung ^a   Mudge, Trevor ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Instruction Level Parallelism; Low Power; Out of order Processor; Register File; Write Queue

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SYSTEMS; DATA STORAGE EQUIPMENT; ENERGY DISSIPATION; ENERGY UTILIZATION; MECHANICAL CLOCKS; PIPELINE PROCESSING SYSTEMS; PROBLEM SOLVING;

INSTRUCTION LEVEL PARALLELISM; LOW POWER; OUT-OF-ORDER PROCESSORS; REGISTER FILES; WRITTE QUEUE;

MICROPROCESSOR CHIPS;

EID: 1142280977     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/782814.782839     Document Type: Conference Paper

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