Reducing operand transport complexity of superscalar processors using distributed register files

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 532-535

  Bunchua, Santithorn ^a   Wills, D Scott ^a   Wills, Linda M ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; DATA TRANSFER; MULTIMEDIA SYSTEMS; PROGRAM PROCESSORS; RESPONSE TIME (COMPUTER SYSTEMS);

OPERAND BYPASS NETWORK; REGISTER FILE; SUPERSCALAR PROCESSORS;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 0345412726     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. K.I. Farkas, et al, "The Multicluster Architecture: Reducing Cycle Time through Partitioning," Proc. of the 30th Int. Symp. on Microarchitecture, December 1997.
2. A. Baniasadi and A. Moshovos, "Instruction Distribution Heuristics for Quad-Cluster, Dynamically Scheduled, Superscalar Processors," Proc. of the 33rd Int. Symp. on Microarchitecture, December 2000.
3. J.M. Parcerisa and A. González, "Reducing Wire Delay Penalty through Value Prediction," Proc. of the 33rd Int. Symp. on Microarchitecture, December 2000.
4. M. Franklin and G.S. Sohi, "Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors," Proc. of the 25th Int. Symp. on Microarchitecture, December 1992.
5. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling," IEEE Computer, vol. 35, no. 2, February 2002.
6. P. Shivakumar and N. Jouppi, "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model," Compaq WRL Research Report 2001/2, August 2001.
7. S. Palacharla, N.P. Jouppi, and J.E. Smith, "Complexity-Effective Superscalar Processors," Proc. of the 24th Int. Symp. on Computer Architecture, 1997.