The challenges of massive on-chip concurrency

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3740 LNCS, Issue , 2005, Pages 157-170

  Bousias, Kostas ^a   Jesshope, Chris ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT COMPLEXITY; MICROGRIDS; ON-CHIP RESOURCES; POWER DISSIPATION;

CLOCKS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); TRANSISTORS;

CONCURRENCY CONTROL;

EID: 33646534810     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11572961_14     Document Type: Conference Paper

References (29)

1. I .C Jesshope (2004) Micro-grids - the exploitation of massive on-chip concurrency, invited paper, Cetraro HPC workshop 2004, Cetraro, Italy, to be published in Advances in Parallel Computing, 2005 (http://staff.science.uva.nl/ ~jesshope/Papers/HPC-paper.pdf)
2. D W Anderson, F J Sparacio, R M Tomasulo (1967) The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling, IBM J. Res. Dev., 11, Number 1, p8.
3. J Smith and A Pleszkun (1985) Implementation of Precise Interrupts in Pipelined Processors, in Proc. of Int'l. Symposium on Computer Architecture, pp.36-44.
4. 4.G Kucuk, D Ponomarev, K Chose and P M Kogge (2001) Energy-Efficient Instruction Dispatch Buffer Design, in Int'l. Symp. on Low Power Electronics and Design (ISLPED'01), August 2001.
5. R Balasubramonian, S Dwarkadas and D Albonesi (2001) Reducing the Complexity of the Register File in Dynamic Superscalar Processor, in Proc. of the 34th Int'l. Symposium on Microarchitecture (MICRO'01), p37.
6. 6.A Shilov (2004) Intel to Cancel NetBurst, Pentium 4, Xeon Evolution, http://www.xbitlabs.com/news/cpu/display/20040507000306.html, accessed 7/1/2005.
7. 7.K Wilcox and S Manne (1999) Alpha processors: A history of power issues and a look to the future, Cool-Chips Tutorial, November 1999. Held in conjunction with MICRO-32.
8. 8.M Homewood, D May, D Shepherd and R Shepherd (1987) The IMS T800 Transputer IEEE Micro, October 1987, pp10-26.
9. 9.R H J M Otten and P Stravers (2000) Challenges in physical chip design, Proc. ICCAD '00, p84, San Jose, California, IEEE Computer society press.
10. R Ronen, A Mendelson, K Lai, F Pollack and J Shen (2001) Coming challenges in Microarchitecture and architecture. Proc IEEE, 89 (3), pp325-40.
11. A Bolychevsky, C R Jesshope and V B Muchnick, (1996) Dynamic scheduling in RISC architectures, IEE Trans. E, Computers and Digital Techniques , 143, pp309-317
12. A Gontmakher and A Schuster (2002) Intrathreads: Techniques for Parallelizing Sequential Code, 6th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC-6), November 2002, Istanbul (in conjunction with Micro-35).
13. C. R. Jesshope and B. Luo (2000) Micro-threading: A New Approach to Future RISC, Proc ACAC 2000, pp34-41, ISBN 0-7695-0512-0 (IEEE Computer Society press), Canberra Jan 2000.
14. Jesshope, C. R. (2001) Implementing an efficient vector instruction set in a chip multiprocessor using micro-threaded pipelines, Proc. ACS AC 2001, Australia Computer Science Communications, 23, No 4., pp80-88, IEEE Computer Society (Los Alimitos, CA, USA), ISBN 0-7695-0954-1.
15. Luo B. and Jesshope C. (2002) Performance of a Micro-threaded Pipeline, in Proc. 7th Asia-Pacific conference on Computer systems architecture, 6 , (Feipei Lai and John Morris Eds.) Australian Computer Society, Inc. Darlinghurst, Australia, ISBN ∼ ISSN: 1445-1336 , 0-909925-84-4 , pp83-90.
16. Jesshope C. R. (2003) Multithreaded microprocessors - evolution or revolution (Keynote paper), Proc. ACSAC 2003: Advances in Computer Systems Architecture, Omondo and Sedukhin (Eds.), pp 21-45, Springer, LNCS 2823 (Berlin, Germany), ISSN0302-9743, Aizu, Japan, 22-26 Sept 2003.
17. th Int;l. Workshhops, SAMOS 2003, SAMOS 2004, (LNCS 3133, Springer), ISBN 3-540-22377-0, pp383-392, presented Samos, Greece, July 2004.
18. Brockman J. B., Thoziyoor S., Kuntz S. K. and Kogge, P. M. (2004) A low cost, multithreaded processing-in-memory system, Proc. 3rd workshop on Memory performance issues (ISCA 31), ISBN:1-59593-040-X, pp16-22.
19. I Foster, A Roy and V Sander (2000) A Quality of Service Architecture that Combines Resource Reservation and Application Adaptation, Proc. 8th International Workshop on Quality of Service (IWQOS 2000), Pittsburgh, USA.
20. R Buyya and M Murshed, (2002) GridSim: A Toolkit for the Modeling and Simulation of Distributed Resource Management and Scheduling for Grid Computing, Journal of Concurrency and Computation: Practice and Experience (CCPE), 14(13-15), Wiley Press, Nov.-Dec., 2002
21. S Manne, A Klauser, and D Grunwald, (1998) Pipeline Gating: Speculation Control for Energy Reduction, Proc Intl Symp. On ComputerArchitecture (ISCA).
22. D Marculescu (2000) Profile driven Code Execution for Low Power Dissipation, Proc. Intl. Symp. Low Power Electronics and Design.
23. V Zyuban and P Kogge (2000) Optimization of High-Performance Superscalar Architectures for Energy-Delay Product, Proc Intl. Symposium on Low Power Electronics and Design.
24. S Ghiasi, J Casmira and D Grunwald, (2000) Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption, Workshop on Complexity Effective Design. ISCA27.
25. A Iyer and D Marculescu (2001) Power aware microarchitecture resource scaling, Proc Design, automation and test in Europe, Munich, Germany, pp190-6, ISBN:0-7695-0993-2.
26. R Sree, A Settle, I Bratt and D A Connors (2003) Compiler-directed resource management for active code region, Proc. 7th Workshop on Interaction between Compilers and Computer Architecture, February 2003, 5.5.
27. st Conf. On Computing Frontiers archive, Ischia, Italy, pp 240-54 , ISBN:1-58113-741-9.
28. A Shafarenko and S-B Scholz (2005) General Homomorphic overloading. Accepted for publication in LCNS (2005). A preliminary version was submitted to IFL'2004 in Luebeck.
29. A Shafarenko (2003) Stream Processing on the Grid: an Array Stream Transforming Language. SNPD 2003: 268-276.