Scalable instruction-level parallelism

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3133, Issue , 2004, Pages 383-392

  Jesshope, Chris ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS; MICROPROCESSOR CHIPS;

CHIP MULTIPROCESSOR; DISTRIBUTED IMPLEMENTATION; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION-LEVEL; MODEL RESULTS; OUT OF ORDER; REGISTER FILES; SCALING PROPERTIES;

NETWORK ARCHITECTURE;

EID: 35048821019     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-27776-7_40     Document Type: Article

References (11)

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8. C Zilles and G Sohi (2001) Execution-based prediction using speculative slices, Proc. Intl. Symposium on Computer Architecture.
9. D Burger and J R Goodman (2004) Billion-transistor architectures: there and back again, IEEE Computer, 37, 3, pp22-28.
10. C R Jesshope (2004) Microthreading, a model for distributed instruction-level concurrency, submitted to Parallel Processing Letters (on-line at: http://www2.dcs.hull.ac.uk/people/csscrj/papers.html).
11. A Lines(2004) Asynchronous interconnect for synchronous SoC design, IEEE Micro, 24, 1, pp32-41.