Architecture of the atlas chip-multiprocessor: dynamically parallelizing irregular applications

IEEE Transactions on Computers

Volumn 50, Issue 1, 2001, Pages 67-82

  Codrescu, Lucian ^a,b   Wills, D Scott ^a,b   Meindl, James ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURAL STRUCTURES; MULTITHREADING; SINGLE CHIP MULTIPROCESSORS; THREAD SPECULATION; VALUE PREDICTION;

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

COMPUTER ARCHITECTURE;

EID: 0035104225     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.902753     Document Type: Article

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