Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 64-67

  Mukhopadhyay, Saibal ^a   Mahmoodi Meimand, Hamid ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; MOS DEVICES; MOSFET DEVICES; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS; TRANSISTORS;

FAILURE PROBABILITY; PARAMETER VARIATIONS; SRAM CELLS; YIELD ENHANCEMENT;

STATIC RANDOM ACCESS STORAGE;

EID: 4544332286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. http://www-mtl.mit.edu/Well/
3. S. Mukhopadhyay, et. al., DAC, pp. 169-174, June 2003
4. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices
5. MEDICI: 2-D device simulation program, Synopsys Inc.
6. A. Papoulis, Probability, Random Variables and Stochastic Process
7. A. Chandrakasan, Design of High-Performance Microprocessor Circuits
8. H. Kato, et. al., IEEE JSSC, pp. 232-237, February 1997.