Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 410-415

  Mukhopadhyay, Saibal ^a   Kim, Keunwoo ^b   Kim, Jae Joon ^b   Lo, Shih Hsien ^b   Joshi, Rajiv V ^b   Chuang, Ching Te ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS AND CONTROLS; DOUBLE-GATE DEVICE; GATE LEAKAGES; GATE TUNNELING; MODEL AND ANALYSIS; POLYSILICON GATES; TRANSISTOR DESIGNS; ULTRA-THIN OXIDE;

DESIGN;

MOS DEVICES;

EID: 84886710336     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.77     Document Type: Conference Paper

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