Safety property verification using sequential SAT and bounded model checking

IEEE Design and Test of Computers

Volumn 21, Issue 2, 2004, Pages 132-143

  Parthasarathy, Ganapathy ^a   Iyer, Madhu K ^a   Cheng, Kwang Ting Tim ^b   Wang, Li C ^a  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; FUNCTION EVALUATION; MATHEMATICAL OPERATORS;

DESIGN VERIFICATION; DIGITAL HARDWARE; FUNCTIONAL VERIFICATION;

COMPUTER HARDWARE;

EID: 1942500401     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.1277906     Document Type: Article

References (9)

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