Design rewiring using ATPG

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 12, 2002, Pages 1469-1479

  Veneris, Andreas ^a   Abadir, Magdy S ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b MOTOROLA INC   (United States)

Author keywords

CAD; Diagnosis; Synthesis; Testing; VLSI

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; OPTIMIZATION; PATTERN RECOGNITION;

AUTOMATED TEST PATTERN GENERATION (ATPG);

VLSI CIRCUITS;

EID: 0036909146     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804388     Document Type: Article

References (25)

1. M.S. Abadir, J. Ferguson, and T.E. Kirkland, "Logic verification via test generation," IEEE Trans. Computer-Aided Design, vol. 7, pp. 138-148, Jan. 1988.
2. R.E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
3. S.C. Chang and Z.Z. Wu, "Theory and extensions of single wire replacement," IEEE Trans. Computer-Aided Design, vol. 20, pp. 1159-1163, Sept. 2001.
4. S.C. Chang, K.T. Chang, N.S. Woo, and M. Marek-Sadowska, "Post-layout logic restructuring using alternative wires," IEEE Trans. Computer-Aided Design, vol. 16, pp. 587-596, June 1997.
5. S.C. Chang and M. Marek-Sadowska, "Perturb and simplify: Multilevel Boolean network optimizer," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 2-5.
6. S.C. Chang, J.C. Chuang, and Z.Z. Wu, "Synthesis for multiple input wires replacement of a gate for wiring consideration," in Proc. Int. Conf Computer-Aided Design, 1999, pp. 115-118.
7. M. Chatterjee, D. Pradham, and W. Kunz, "LOT: Logic optimization with testability - New transformations using recursive learning," in Proc. Int. Conf. Computer-Aided Design, 1995, pp. 115-118.
8. R. Dandapani and S.M. Reddy, "On the design of logic networks with redundancy and testability considerations," IEEE Trans. Comput., vol. C-23, Nov. 1974.
9. J.A. Espejo, L. Entrena, E. San Millàn, and E. Olìas, "Functional extension of structural logic optimization techniques," in Proc. Asian-South-Pacific Design Automation Conf., 2001, pp. 467-472.
10. L.A. Entrena and K.T. Chang, "Combinational and sequential logic optimization by redundancy addition and removal," IEEE Trans. Computer-Aided Design, vol, 14, pp. 909-916, July 1995.
11. H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. Comput., vol. C-32, Dec. 1983.
12. I. Hamzaoglu and J.H. Patel, "New techniques for deterministic test pattern generation," in Proc. VLSI Test Symp., 1998, pp. 446-452.
13. T. Kirkland and M.R. Mercer, "A topological search algorithm for ATPG," in IEEE Design Automation Conf., 1987, pp. 502-508.
14. W. Kunz and D.K. Pradhan, "Recursive learning: A new implication technique for efficient solutions to CAD problems-test, verification, and optimization," IEEE Trans. Computer-Aided Design, vol 13, pp. 1143-1158, Sept. 1994.
15. W. Kunz, D. Stoffel, and P.R. Menon, "Logic optimization and equivalence checking by implication analysis," IEEE Trans. Computer-Aided Design, vol. 16, pp. 266-281, Mar. 1997.
16. Y.M. Jiang, A. Krstic, K.T. Chang, and M. Marek-Sadowska, "Post-layout logic restructuring for performance optimization," in IEEE Design Automation Conf., 1997, pp. 662-665.
17. B. Rohfleisch, A. Kolbl, and B. Wurth, "Reducing power dissipation after technology mapping by structural transformations," in Proc. Design Automation Conf., 1996, pp. 789-794.
18. J.P. Roth, "Diagnosis of automata failures: A calculus and a method," IBM J. Res. Development, vol. 10, pp. 278-291, June 1966.
19. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, 1992, pp. 328-333.
20. M.H. Schulz and E. Auth, "Improved deterministic test pattern generation with applications to redundancy identification," IEEE Trans. Computer-Aided Design, vol. 8, pp. 811-816, July 1989.
21. J.E. Smith, "On necessary and sufficient conditions for multiple fault undetectability," IEEE Trans. Comput., vol. c-28, pp. 801-802, Oct. 1979.
22. G. Stenz, B.M. Riess, B. Rohfleisch, and F.M. Johannes, "Performance optimization by interacting netlist transformations and placement," IEEE Trans. Computer-Aided Design, vol. 19, Mar. 2000.
23. A. Veneris and I.N. Hajj, "Design error diagnosis and correction via test vector simulation," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1803-1816, Dec. 1999.
24. A. Veneris, M.S. Abadir, and I. Ting, "Design rewiring based on diagnosis techniques," in Proc. Asian-South-Pacific Design Automation Conf., 2001, pp. 479-484.
25. A. Veneris, M. Amiri, and I. Ting, "Design rewiring for power minimization," in IEEE Int. Symp. Circuits Systems, 2002.