FPGA routing and routability estimation via Boolean satisfiability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 2, 1998, Pages 222-231

  Wood, R Glenn ^b   Rutenbar, Rob A ^a,c  

^a IEEE

^b HEWLETT PACKARD COMPANY   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Computer aided design; Field programmable gate array (FPGA); Placement; Rapid prototype; Routing

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DECISION TABLES; LOGIC CIRCUITS; RAPID PROTOTYPING;

BINARY DECISION DIAGRAMS (BDD); FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0032095693     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.678873     Document Type: Article

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