Diagnosing realistic bridging faults with single stuck-at information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 3, 1998, Pages 255-268

  Lavo, David B ^a,b   Chess, Brian ^b,c   Larrabee, Tracy ^a,b   Ferguson, F Joel ^a,b  

^a Department of IEEE ^*  (United States)

^b University of California Santa Cruz   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; MATHEMATICAL MODELS;

FAULT DIAGNOSIS; MATCH RANKING; MATCH REQUIREMENT; MATCH RESTRICTION;

INTEGRATED CIRCUIT TESTING;

EID: 0032024307     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.700723     Document Type: Article

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