Speeding up the Byzantine fault diagnosis using symbolic simulation

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 193-198

  Huang, Shi Yu ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Cause effect analysis; Central Processing Unit; Circuit faults; Circuit simulation; Dictionaries; Fault diagnosis; Logic gates; Manufacturing; Silicon; Voltage

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; FAILURE ANALYSIS; GLOSSARIES; LOGIC CIRCUITS; LOGIC GATES; MANUFACTURE; MODEL CHECKING; PROGRAM PROCESSORS; SILICON; VLSI CIRCUITS;

BENCHMARK CIRCUIT; BYZANTINE FAULT; CAUSE-EFFECT ANALYSIS; CIRCUIT FAULTS; IMPLICIT ENUMERATION; ORDERS OF MAGNITUDE; POTENTIAL FAULTS; SYMBOLIC SIMULATION;

FAULT DETECTION;

EID: 84948442818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011138     Document Type: Conference Paper

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