Finding good counter-examples to aid design verification

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 51-52

  Fey, G ^a   Dreschler, R ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

Boolean functions; Circuits; Computer science; Costs; Data structures; Debugging; Error correction; Formal verification; Guidelines; Testing

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER DEBUGGING; COMPUTER SCIENCE; COSTS; DATA STRUCTURES; ERROR CORRECTION; FORMAL METHODS; FORMAL VERIFICATION; NETWORKS (CIRCUITS); TESTING;

COUNTER EXAMPLES; DESIGN COSTS; DESIGN ERRORS; DESIGN VERIFICATION; GUIDELINES; VERIFICATION TOOLS;

DESIGN;

EID: 24144498989     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210088     Document Type: Conference Paper

References (5)

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