CMOS transistor mismatch model valid from weak to strong inversion

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 627-630

  Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabé ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS MODELING; CURRENT MISMATCH; DIFFERENT GEOMETRY; MEAN RELATIVE ERROR; MISMATCH CHARACTERIZATION; PMOS TRANSISTORS; STRONG INVERSION REGIONS; WEAK INVERSION REGION;

EID: 84893720956     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257213     Document Type: Conference Paper

References (6)

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2. M. J. M. Pelgrom, A. C. J. Dninmaijer, and A. P. G. Welbers, "Matching Properties of MOS Transistors, " IEEE Journal of Solid State Circuits, vol. 24, No. 5, pp. 1433-1440, 1989.
3. J. Bastos, Characterization of MOS Transistor Mismatch for Analog Design, Ph. D. Dissertation, Katholieke Universiteit Leuven, 1998.
4. J. Croon, M. Rosmeulen, S. Decoutete, and W. Sansen, "An Easy-to-Use Mismatch Model for the MOS Transistor, " IEEE Journal of Solid State Circuits, vol. 37, No. 8, pp. 1056-1064, August, 2002.
5. C. C. Enz, F. Krummernacher and E. A. Vittoz, "An Analytical MOS Transistor Model Valid for All Regions of Operation and Dedicated to Low-Voltage Low-Current Applications, " Analog Integrated Circuits and Signal Processing Journal, vol. 8, pp 83-114, July 1995.
6. C. Galup-Montoro, M. C. Schneider and A. I. A. Cunha, "A Current-Based MOSFET Model for Integrated Circuit Design", Chapter 1 in Low- Voltage/Low-Power Integrated Circuits and Systems, edited by E. Sanchez-Sinencio and A. G. Andreou, IEEE Press, August 1998.