메뉴 건너뛰기




Volumn 3, Issue 4, 2003, Pages 6-17

Interconnect Noise Analysis and Optimization in Deep Submicron Technology

Author keywords

[No Author keywords available]

Indexed keywords

COUPLING FREE ROUTING (CFR); DEEP SUBMICRON TECHNOLOGY; INTERCONNECT NOISE ANALYSIS;

EID: 2342595782     PISSN: 1531636X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCAS.2003.1267064     Document Type: Article
Times cited : (44)

References (49)
  • 1
    • 84862343889 scopus 로고    scopus 로고
    • Available: http://www.synopsys.com/products/tlr/flexroute_wp.pdf.
  • 2
    • 84862353948 scopus 로고    scopus 로고
    • Available: http://public.itrs.net/files/1999_SIA_Roadmap/Int.pdf.
  • 4
    • 0025435021 scopus 로고
    • Projecting interconnect electromigration lifetime for arbitrary current waveforms
    • May
    • B.K. Liew, N.W. Cheung, and C. Hu, "Projecting interconnect electromigration lifetime for arbitrary current waveforms," IEEE Trans. Electron Devices, vol. 37, May 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37
    • Liew, B.K.1    Cheung, N.W.2    Hu, C.3
  • 5
    • 0031236706 scopus 로고    scopus 로고
    • High-current failure model for VLSI interconnects under short-pulse stress conditions
    • Sept.
    • K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu, "High-current failure model for VLSI interconnects under short-pulse stress conditions," IEEE Electron Device Lett., vol. 18, Sept. 1997.
    • (1997) IEEE Electron Device Lett. , vol.18
    • Banerjee, K.1    Amerasekera, A.2    Cheung, N.3    Hu, C.4
  • 6
    • 0029700866 scopus 로고    scopus 로고
    • Characterization of VLSI circuit interconnect heating and failure under ESD conditions
    • Dallas, TX, Apr.-May
    • K. Banerjee, A. Amerasekera, and C. Hu, "Characterization of VLSI circuit interconnect heating and failure under ESD conditions," in Proc. Int. Reliability Physics Symp., Dallas, TX, Apr.-May 1996.
    • (1996) Proc. Int. Reliability Physics Symp.
    • Banerjee, K.1    Amerasekera, A.2    Hu, C.3
  • 8
    • 0031079046 scopus 로고    scopus 로고
    • Self-consistent solutions for allowed interconnect current density - Part I: Implications for technology evolution
    • Feb.
    • W.R. Hunter, "Self-consistent solutions for allowed interconnect current density - Part I: Implications for technology evolution," IEEE Trans. Electron Devices, vol. 44, Feb. 1997.
    • (1997) IEEE Trans. Electron Devices , vol.44
    • Hunter, W.R.1
  • 10
  • 12
    • 0032646416 scopus 로고    scopus 로고
    • Information-theoretic bounds on average signal transition activity
    • Sept.
    • S. Ramprasad, N.R. Shanbhag, and I.N. Hajj, "Information-theoretic bounds on average signal transition activity," IEEE Trans. VLSI Syst., Sept. 1999.
    • (1999) IEEE Trans. VLSI Syst.
    • Ramprasad, S.1    Shanbhag, N.R.2    Hajj, I.N.3
  • 14
    • 0032259264 scopus 로고    scopus 로고
    • An alternative architecture for on-chip global interconnect: Segmented bus power modeling
    • Y. Zhang, W. Ye, and M.J. Irwin, "An alternative architecture for on-chip global interconnect: Segmented bus power modeling," in Proc. Asilomar Conf. Signals, Systems, Computers, 1998, pp. 1062-1065.
    • (1998) Proc. Asilomar Conf. Signals, Systems, Computers , pp. 1062-1065
    • Zhang, Y.1    Ye, W.2    Irwin, M.J.3
  • 15
    • 0032683154 scopus 로고    scopus 로고
    • Power estimation for architectural exploration of HW/SW communication on system-level buses
    • W. Fornaciari, D. Sciuto, and C. Silvano, "Power estimation for architectural exploration of HW/SW communication on system-level buses," in Proc. M. Workshop Hardware/Software Codesign, 1999, pp. 152-156.
    • (1999) Proc. M. Workshop Hardware/Software Codesign , pp. 152-156
    • Fornaciari, W.1    Sciuto, D.2    Silvano, C.3
  • 16
    • 0025414182 scopus 로고
    • Asymptotic waveform evaluation for timing analysis
    • Apr.
    • L.T. Pillage and R.A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
    • (1990) IEEE Trans. Computer-aided Design , vol.9 , pp. 352-366
    • Pillage, L.T.1    Rohrer, R.A.2
  • 17
    • 2342625669 scopus 로고    scopus 로고
    • Interconnect-driven floorplanning with fast global wiring planning and optimization
    • Phoenix, AZ, Sept.
    • C.C. Chang, J. Cong, D. Zhigang, and X. Yuan, "Interconnect-driven floorplanning with fast global wiring planning and optimization," in Proc. SRC Techcon Conf., Phoenix, AZ, Sept. 2000, pp. 21-23.
    • (2000) Proc. SRC Techcon Conf. , pp. 21-23
    • Chang, C.C.1    Cong, J.2    Zhigang, D.3    Yuan, X.4
  • 18
    • 0033716473 scopus 로고    scopus 로고
    • A timing model incorporating the effect of crosstalk on delay and its application to optimal channel
    • May
    • S.S. Sapatnekar, "A timing model incorporating the effect of crosstalk on delay and its application to optimal channel," IEEE Trans. Computer-Aided Design, vol. 19, May 2000.
    • (2000) IEEE Trans. Computer-aided Design , vol.19
    • Sapatnekar, S.S.1
  • 20
    • 0035335058 scopus 로고    scopus 로고
    • Wire packing-a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution
    • May
    • R. Kay and R.A. Rutenbar, "Wire packing-a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution," IEEE Trans. Computer-Aided Design, vol. 20, May 2001.
    • (2001) IEEE Trans. Computer-aided Design , vol.20
    • Kay, R.1    Rutenbar, R.A.2
  • 21
    • 0034229328 scopus 로고    scopus 로고
    • Simultaneous routing and buffer insertion with restrictions on buffer locations
    • July
    • H. Zhou, D.F. Wong, I-Min Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," IEEE Trans. Computer-Aided Design, vol. 19, July 2000.
    • (2000) IEEE Trans. Computer-aided Design , vol.19
    • Zhou, H.1    Wong, D.F.2    Liu, I.-M.3    Aziz, A.4
  • 24
    • 0032307685 scopus 로고    scopus 로고
    • Getting to the bottom of deep submicron
    • D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in Proc. ICCAD, 1998, pp. 203-211.
    • (1998) Proc. ICCAD , pp. 203-211
    • Sylvester, D.1    Keutzer, K.2
  • 27
    • 0032643013 scopus 로고    scopus 로고
    • Reducing cross-coupling among interconnect wires in deep-submicron datapath design
    • New Orleans, LA, June
    • J.S. Yim and C.M. Kyung, "Reducing cross-coupling among interconnect wires in deep-submicron datapath design," in Proc. 36th Design Automation Conf. (DAC), New Orleans, LA, June 1999, pp. 485-490.
    • (1999) Proc. 36th Design Automation Conf. (DAC) , pp. 485-490
    • Yim, J.S.1    Kyung, C.M.2
  • 28
    • 0012979895 scopus 로고    scopus 로고
    • Simultaneous shield insertion and net ordering
    • San Diego, CA, Apr. 9-12
    • L. He and K.M. Lepak, "Simultaneous shield insertion and net ordering," in Proc. Int. Symp. Physical Design, San Diego, CA, Apr. 9-12, 2000.
    • (2000) Proc. Int. Symp. Physical Design
    • He, L.1    Lepak, K.M.2
  • 29
  • 30
  • 33
    • 84862353953 scopus 로고    scopus 로고
    • Available: http://developer.intel.com/technology/itj/q12001/articles/ art_5.htm.
  • 34
    • 0027222295 scopus 로고
    • Closed-form expression for interconnect delay, coupling, and crosstalk in VLSIs
    • Jan.
    • T. Sakurai, "Closed-form expression for interconnect delay, coupling, and crosstalk in VLSIs," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , pp. 118-124
    • Sakurai, T.1
  • 35
    • 0031349694 scopus 로고    scopus 로고
    • An analytical delay model for RLC interconnects
    • Dec.
    • A.B. Kahng and S. Muddu, "An analytical delay model for RLC interconnects," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1507-1514, Dec. 1997.
    • (1997) IEEE Trans. Computer-aided Design , vol.16 , pp. 1507-1514
    • Kahng, A.B.1    Muddu, S.2
  • 36
    • 0034187951 scopus 로고    scopus 로고
    • Experimental characterization and modeling of transmission line effects for high-speed VLSI circuits interconnects
    • May
    • W. Jin, et al., "Experimental characterization and modeling of transmission line effects for high-speed VLSI circuits interconnects," IEICE Trans. Electron, vol. E83-C, pp. 728-735, May 2000.
    • (2000) IEICE Trans. Electron , vol.E83-C , pp. 728-735
    • Jin, W.1
  • 39
    • 85030259511 scopus 로고    scopus 로고
    • Noise and delay uncertainty studies for coupled RC interconnects
    • Sept.
    • A.B. Kahng, S. Muddu, and D. Vidhani, "Noise and delay uncertainty studies for coupled RC interconnects," in Proc. IEEE Int. ASIC/SOC Conf., Sept. 1999, pp. 3-8.
    • (1999) Proc. IEEE Int. ASIC/SOC Conf. , pp. 3-8
    • Kahng, A.B.1    Muddu, S.2    Vidhani, D.3
  • 45
    • 0027832525 scopus 로고
    • Optimal wire sizing under the distributed elmore delay model
    • J. Cong and K.S. Leung, "Optimal wire sizing under the distributed elmore delay model," in Proc. Int. Conf. Computer Aided Design, 1993, pp. 634-639.
    • (1993) Proc. Int. Conf. Computer Aided Design , pp. 634-639
    • Cong, J.1    Leung, K.S.2
  • 46
    • 0027206875 scopus 로고
    • Performance-driven interconnect design based on distributed RC model
    • J. Cong, K.S. Leung, and D. Zhou, "Performance-driven interconnect design based on distributed RC model," in Proc. Design Automation Conf., 1993, pp. 606-611.
    • (1993) Proc. Design Automation Conf. , pp. 606-611
    • Cong, J.1    Leung, K.S.2    Zhou, D.3
  • 48
    • 0034847877 scopus 로고    scopus 로고
    • Simultaneous shield insertion and net ordering under explicit RLC noise constraint
    • K.M. Lepak, I. Luwandi, and L. He, "Simultaneous shield insertion and net ordering under explicit RLC noise constraint," in Proc. Design Automation Conf., 2001, pp. 199-202.
    • (2001) Proc. Design Automation Conf. , pp. 199-202
    • Lepak, K.M.1    Luwandi, I.2    He, L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.