High-current failure model for VLSI interconnects under short-pulse stress conditions

IEEE Electron Device Letters

Volumn 18, Issue 9, 1997, Pages 405-407

  Banerjee, Kaustav ^a,c   Amerasekera, Ajith ^b,c   Cheung, Nathan ^a,c   Hu, Chenming ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; CURRENT DENSITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; METALLIZING; OXIDES; PULSE WIDTH MODULATION; RELIABILITY; STRESS ANALYSIS; TITANIUM COMPOUNDS; VLSI CIRCUITS;

INTEGRATED CIRCUIT INTERCONNECTS; SHORT PULSE STRESS;

INTERCONNECTION NETWORKS;

EID: 0031236706     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.622511     Document Type: Article

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