Simultaneous routing and buffer insertion with restrictions on buffer locations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 7, 2000, Pages 819-824

  Zhou, Hai ^a   Wong, D F ^b   Liu, I Min ^c   Aziz, Adnan ^c  

^a SYNOPSYS INC   (United States)

^b University of Technology   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; DELAY CIRCUITS; INSERTION LOSSES; MATHEMATICAL MODELS; POLYNOMIALS; PROBLEM SOLVING;

BUFFER INSERTION PROBLEM; BUFFER LOCATION RESTRICTION; ELMORE DELAY MODELS; INTEGRATED CIRCUIT INTERCONNECTIONS; POLYNOMIAL TIME EXACT ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034229328     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.851998     Document Type: Article

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