Characterization of VLSI circuit interconnect heating and failure under ESD conditions

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1996, Pages 237-245

  Banerjee, Kaustav ^a   Amerasekera, Ajith ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL CURRENTS; ELECTRIC DISCHARGES; ELECTRIC WIRING; ELECTROMIGRATION; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RELIABILITY; THERMAL EFFECTS;

CRITICAL FAILURE CURRENT; ELECTROSTATIC DISCHARGES; INTERCONNECT METALLIZATION; LATENT ELECTROSTATIC DISCHARGE DAMAGE; THERMAL BREAKDOWN; TRANSMISSION LINE PULSING SYSTEM;

VLSI CIRCUITS;

EID: 0029700866     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/relphy.1996.492126     Document Type: Conference Paper

References (18)