A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 5, 2000, Pages 550-559

  Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

Capacitive coupling; Crosstalk; Delay; Simulation, timing

Indexed keywords

CHANNEL ROUTING; DELAY; OBJECTIVE FUNCTION; TIMING MODEL;

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; HEURISTIC METHODS; ITERATIVE METHODS; POLYNOMIALS; SIMULATED ANNEALING; THEOREM PROVING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033716473     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.845079     Document Type: Article

References (22)

1. D. H. Xie and M. NakhlaDelay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations, IEEE Trans. Computer-Aided Design, vol. 12, pp. 1798-1811, Nov. 1993.
2. T. Gao and C. L. LiuMinimum crosstalk channel routing, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1993, pp. 692-696.
3. _Minimum crosstalk switchbox routing, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 610-615.
4. K. Chaudhary, A. Onozawa, and E. S. KuhA spacing algorithm for performance enhancement and cross-talk reduction, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1993, pp. 697-702.
5. D. A. Kirkpatrick and A. L. Sangiovanni-VincentelliTechniques for crosstalk avoidance in the physical design of high-performance digital systemsin Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 616-619.
6. T. Xue, E. S. Kuh, and D. WangPost global routing crosstalk risk estimation and reduction, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 302-309.
7. H. Zhou and D. F. WongGlobal routing with crosstalk constraints, in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 374-377.
8. A. DevganEfficient coupled noise estimation for on-chip interconnects, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 147-151.
9. K. Shepard, V. Narayanan, P. C. Elmendorf, and G. ZhengGlobalHarmony: Coupled noise analysis for full-chip RC interconnect networks, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 139-146.
10. P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. PileggiDetermination of worst case aggressor alignment for delay calculation, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1998, pp. 212-219.
11. K.-S. Jhang, S. Ha, and C. S. JhonCOP: A crosstalk Optimizer for gridded channel routing, IEEE Trans. Computer-Aided Design, vol. 15, pp. 424-429, Apr. 1996.
12. L. GalOn-chip cross talk-The new signal integrity challenge, in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 251-254.
13. F. Dartu and L. T. PileggiCalculating worse-case gate delays due to dominant capacitance coupling, in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 46-51.
14. J. CongChallenges and opportunities for design innovations in nanometer technologies, Semiconductor Research Corporation, Research Triangle Park, NC, http://www.src.org/cgi-bin/deIiver.cgi/p_s98005.pdf?/pubs/opendocs/p_s98005.pdf, 1997.
15. S. S. SapatnekarandS. M. Kang, Design Automation for Timing-Driven Layout Synthesis. Norwell, MA: Kluwer Academic, 1993.
16. T. Yoshimura and E. S. KuhEfficient algorithms for channel routing, lEEETrans. Computer-AidedDesign,vol.CAD-l,pp.25-35,Jan. 1982.
17. N. Sherwani, Algorithms for VLSI Physical Design Automation. Norwell, MA: Kluwer Academic, 1995.
18. J. Lillis, C. K. Cheng, and T.-T. LinOptimal wire sizing and buffer insertion for low power and a generalized delay model, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1995, pp. 138-143.
19. L. P. P. van GinnekenBuffer placement in distributed RC-tree networks for minimal Elmore delay, in Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 865-867.
20. A. Tucker, Applied Combinatorics, 2nd ed. New York: Wiley, 1984.
21. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. New York: McGraw Hill, 1990.
22. S. Kirkpatrick, C. Gelatt, Jr., and M. VecchiOptimization by simulated annealing, Science, vol. 220, pp. 671-680, May 1983.