Simultaneous routing and buffer insertion for high performance interconnect

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 148-153

  Lillis, J ^a   Cheng, Ch K ^a   Lin, T T Y ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; EFFICIENCY; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; PERFORMANCE; TOPOLOGY;

ROUTING;

VLSI CIRCUITS;

EID: 0029716943     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)