Reducing cross-coupling among interconnect wires in deep-submicron datapath design

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 485-490

  Yim, Joon Seo ^a   Kyung, Chong Min ^a  

^a LG   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; ELECTRIC WIRE; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL PROGRAMMING;

CROSS-COUPLING EFFECTS; EVOLUTIONARY PROGRAMMING; INTERCONNECT WIRES;

CMOS INTEGRATED CIRCUITS;

EID: 0032643013     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309984     Document Type: Conference Paper

References (19)