Driver modeling and alignment for worst-case delay noise

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 720-725

  Sirichotiyakul, S ^a   Blaauw, D ^a   Oh, C ^a   Levy, R ^a   Zolotov, V ^a   Zuo, J ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DELAY CIRCUITS; ERROR ANALYSIS; LOGIC GATES; SWITCHING THEORY;

CROSS COUPLING CAPACITANCE; DRIVER MODELING;

SPURIOUS SIGNAL NOISE;

EID: 0034841570     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.379054     Document Type: Conference Paper

References (9)

1. Global harmony: Coupled noise analysis for full-chip RC interconnect networks
2. PRIMA: Passive reduced-order interconnect macromodeling algorithm
3. Performance computation for precharacterized CMOS gates with RC loads
4. Modeling the effective capacitance for the RC interconnect of CMOS gates
5. Calculating worst-case gate delays due to dominant capacitance coupling
6. Determination of worst-case aggressor alignment for delay calculation
7. Clarinet: A noise analysis tool for deep submicron design
8. Capturing the effect of crosstalk on delay
9. TACO: Timing analysis with coupling