System level validation using formal techniques

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 3, 2005, Pages 393-406

  Drechsler, R ^a   Grosse D ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LANGUAGE TRANSLATION; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COSTS; INTEGRATED CIRCUIT LAYOUT; OBJECT ORIENTED PROGRAMMING; PROGRAM DEBUGGING;

BOUNDED MODEL CHECKING (BMC); EQUIVALENCE CHECKING (EC); FORMAL VERIFICATION; MODEL CHECKING (MC);

COMPUTATIONAL COMPLEXITY;

EID: 22944455550     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045073     Document Type: Conference Paper

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