Optimized temporal logic compilation

Journal of Universal Computer Science

Volumn 9, Issue 2, 2003, Pages 120-137

  Krebs, Andreas ^a   Ruf, Jürgen ^a  

^a UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

Emulation; Simulation; System Level; Temporal Logic; Verification

Indexed keywords

EID: 22944463987     PISSN: 0958695X     EISSN: 09486968     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (14)

1. [Augustin et al. 1988] L.M. Augustin, B.A. Gennart, Y. Huh, D.C. Luckham, and A.G. Stanculescu. Verification of VHDL designs using VAL. In Design Automation Conference (DAC). ACM/IEEE, 1988.
2. [Sugar 2001] Ilan Beer, Shoham Ben-David, Cindy Eisner, Dana Fisman, Anna Gringauze, and Yoav Rodeh. The temporal logic sugar. Lecture Notes in Computer Science, 2001.
3. [Biere et al. 1999] Armin Biere, Alessandro Cimatti, Edmund M. Clarke, and Yunshan Zhu. Symbolic model checking without BDDs. In Tools and Algorithms for Construction and Analysis of Systems, 1999.
4. [Brand 1993] D. Brand. Verification of Large Synthesized Designs. In IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, California, November 1993. ACM/IEEE, IEEE Computer Society Press.
5. 20 States and Beyond. In IEEE Symposium on Logic in Computer Science (LICS), Washington, D.C., June 1990. IEEE Computer Society Press.
6. [Canfield et al. 1997] W. Canfield, E. Emerson, and A. Saha. Checking formal specifications under simulation. In International, Conference on Computer Design (ICCD '97). IEEE Computer Society Press, 1997.
7. [Emerson 1990] E.A. Emerson. Temporal and Modal Logic. In J. van Leeuwen, editor, Handbook of Theoretical Computer Science, volume B, Amsterdam, 1990. Elsevier Science Publishers.
8. [Grötker et al. 2002] T. Grötker, S. Liao, G. Martin, and S. Swan. System design with System C. Kluwer Academic Publishers, 2002.
9. [Nelson and Jones 1994] B.E. Nelson and R.B. Jones. Simulation event pattern checking with proto. In SHDL 1994, 1994.
10. 2 C-Bus Specification Version 2.1, January 2000. http://www.semiconductors.philips.com/ buses/i2c/facts.
11. [Ruf et al. 2001] J. Ruf, D. W. Hoffmann, T. Kropf, and W. Rosenstiel. Simulation-guided property checking based on multi-valued AR-automata. In Design Automation and Test in Europe (DATE). IEEE Conmputer Society Press, 2001.
12. [Synopsys] www.synopsys.com.
13. [Cadence] www.testbuilder.net.
14. [Verisity] www.verisity.com.