SCOPUS 정보 검색 플랫폼

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 744-751

Functional verification for SystemC descriptions using constraint solving

(3) Ferrandi, Fabrizio a Rendine, Michele a Sciuto, Donatella a

a POLITECNICO DI MILANO (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT SOLVERS; CONSTRAINT SOLVING; FINITE STATE MACHINE MODEL; FUNCTIONAL VERIFICATION; HIGH LEVEL DESCRIPTION; SYSTEM MODELING; SYSTEM UNDER TEST; VERIFICATION METHOD;

EXHIBITIONS; LOGIC PROGRAMMING;

TESTING;

EID: 0038111504 PISSN: 15301591 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DATE.2002.998382 Document Type: Conference Paper

Times cited : (35)

References (8)

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- Cheng, K.¹ Krishnakumar, A.S.²

2
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- RT-level TPG exploiting high-level synthesis information
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- Chiusano, S.¹ Corno, F.² Prinetto, P.³

3
- 0033681071
- An application of genetic algorithms and BDDs to functional testing
- F. Ferrandi, A. Fin, F. Fummi, D. Sciuto, "An application of genetic algorithms and BDDs to functional testing" Proceedings International Conference on Computer Design, 2000
- (2000) Proceedings International Conference on Computer Design
- Ferrandi, F.¹ Fin, A.² Fummi, F.³ Sciuto, D.⁴

4
- 0032630766
- Enhancing simulation with bdds and atpg
- M.K. Ganai, A. Aziz, A. Kuehlmann, "Enhancing simulation with BDDs and ATPG", Proceedings 36th Design Automation Conference, 1999
- (1999) Proceedings 36th Design Automation Conference
- Ganai, M.K.¹ Aziz, A.² Kuehlmann, A.³

5
- 0032320508
- Implicit test generation for behavioral VHDL models
- F. Ferrandi, F. Fummi, D. Sciuto, "Implicit test generation for behavioral VHDL models", Proceedings IEEE International Test Conference, 1998
- (1998) Proceedings IEEE International Test Conference
- Ferrandi, F.¹ Fummi, F.² Sciuto, D.³

6
- 0033681620
- Automatic test pattern generation for functional rtl circuits using assignment decision diagrams
- I. Ghosh, M. Fujita, "Automatic test pattern generation for functional RTL circuits using Assignment Decision Diagrams" Proceeding Design Automation Conference, 2000
- (2000) Proceeding Design Automation Conference
- Ghosh, I.¹ Fujita, M.²

7
- 0032640870
- Simulation vector generation from HDL descriptions for observabilityenhanced statement coverage
- F. Fallah, P. Ashar, S. Devadas, "Simulation vector generation from HDL descriptions for observabilityenhanced statement coverage", Proceedings 35th Design Automation Conference, 1999
- (1999) Proceedings 35th Design Automation Conference
- Fallah, F.¹ Ashar, P.² Devadas, S.³

8
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- Generation of design verification test from behavioral programs using path enumeration and constraint programming
- June
- R. Vemuri, R. Kalyanaraman, "Generation of design verification test from behavioral programs using path enumeration and constraint programming"; IEEE Transactions on Very Large Scale Integration Systems, Vol.3, No.2, June 1995
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- Vemuri, R.¹ Kalyanaraman, R.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.