Binary decision diagrams in theory and practice

International Journal on Software Tools for Technology Transfer

Volumn 3, Issue 2, 2001, Pages 112-136

  Drechsler, Rolf ^a   Sieling, Detlef ^b  

^a Corporate Technology Siemens ^*  (Germany)

^b TU DORTMUND UNIVERSITY   (Germany)

Author keywords

Binary decision diagram; Boolean function; Branching program; Data structure; VLSI CAD

Indexed keywords

BINARY DECISION DIAGRAMS (BDDS); BRANCHING PROGRAMS; COMMERCIAL TOOLS; DECISION DIAGRAM; SPECIAL SECTIONS; THEORY AND PRACTICE; VLSI CAD;

BOOLEAN FUNCTIONS; DATA STRUCTURES;

BINARY DECISION DIAGRAMS;

EID: 84896692832     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s100090100056     Document Type: Article

References (138)

1. Aborhey, S.: Binary decision tree test functions. IEEE Trans Comp 27(11): 1461-1465, 1988
2. Akers, S.B.: Binary decision diagrams. IEEE Trans Comp 27: 509-516, 1978
3. Appenzeller, D.P., Kuehlmann, A.: Formal verification of a PowerPC microprocessor. In: Int Conf Comp Design, pp. 79-84, 1995
4. Ashar, P., Devadas, S., Keutzer, K.: Path-delay-fault testability properties of multiplexor-based networks. Integration, VLSI J 15(1): 1-23, 1993
5. Ashenhurst, R.L.: The decomposition of switching functions. In: Int Symp Theor Switching Funct, pp. 74-116, 1959
6. Bahar, R.I., Frohm, E.A., Gaona, C.M., Hachtel, G.D., Macii, E., Pardo, A., Somenzi, F.: Algebraic decision diagrams and their applications. In: Int Conf CAD, pp. 188-191, 1993
7. Becker, B.: Synthesis for testability: Binary decision diagrams. In: Symp Theor Aspects Comp Sci. LNCS 577. Berlin, Heidelberg, New York: Springer-Verlag, 1992, pp. 501-512
8. Becker, B., Drechsler, R.: Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. In: Eur Des Test Conf, p. 592, 1995
9. Becker, B., Drechsler, R., Enders, R.: On the computational power of bit-level and word-level decision diagrams. In: ASP Des Autom Conf, pp. 461-467, 1997
10. Becker, B., Drechsler, R., Theobald, M.: On the implementation of a package for efficient representation and manipulation of functional decision diagrams. IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, pp. 162-169, 1993
11. Becker, B., Drechsler, R., Theobald, M.: On the expressive power of OKFDDs. Formal Methods Syst Des 11(1): 5-21, 1997
12. Becker, B., Drechsler, R., Werchner, R.: On the relation between BDDs and FDDs. Inf Comput 123(2): 185-197, 1995
13. Bern, J., Meinel, C., Slobodov́a, A.: Efficient OBDD-based Boolean manipulation in CAD beyond current limits. In: Des Autom Conf, pp. 408-413, 1995
14. Bern, J., Meinel, C., Slobodova, A.: Some heuristics for generating tree-like FBDD types. IEEE Trans CAD 15: 127-130, 1996
15. Bhattacharya, D., Agrawal, P., Agrawal, V.D.: Test generation for path delay faults using binary decision diagrams. IEEE Trans Comp 44(3): 434-447, 1995
16. Bollig, B., L̈obbing, M., Sauerhoff, M., Wegener, I.: Complexity theoretical aspects of OFDDs. In: Sasao, T., Fujita, M. (eds.): Representations of discrete functions, pp. 249-268. Kluwer Academic, Boston, Mass., USA, 1996
17. Bollig, B., L̈obbing, M., Wegener, I.: Simulated annealing to improve variable orderings for OBDDs. In: Int Workshop Logic Synth, pp. 5.1-5.10, 1995
18. Bollig, B., L̈obbing, M., Wegener, I.: On the effect of local changes in the variable ordering of ordered decision diagrams. Info Process Lett 59: 233-239, 1996
19. Bollig, B., Sauerhoff, M., Sieling, D., Wegener, I.: Hierarchy theorems for kOBDDs and kIBDDs. Theor Comput Sci 205: 45-60, 1998
20. Bollig, B., Wegener, I.: Improving the variable ordering of OB-DDs is NP-complete. IEEE Trans Comp 45(9): 993-1002, 1996
21. Brace, K.S., Rudell, R.L., Bryant, R.E.: Efficient implementation of a BDD package. In: Des Automat Conf, pp. 40-45, 1990
22. Brayton, R.K., Hachtel, G.D., McMullen, C., Sangiovanni-Vincentelli, A.L.: Logic minimization algorithms for VLSI synthesis. Kluwer Academic, Boston, Mass., USA, 1984
23. Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Trans Comp 35(8): 677-691, 1986
24. Bryant, R.E.: On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans Comp 40: 205-213, 1991
25. Bryant, R.E.: Binary decision diagrams and beyond: enabling techniques for formal verification. In: Int Conf CAD, pp. 236-243, 1995
26. Bryant, R.E., Beatty, D., Brace, K., Cho, K., Sheffler, T.: COSMOS: a compiled simulator for MOS circuits. In: Des Au-tom Conf, pp. 9-16, 1987
27. Bryant, R.E., Chen, Y.-A.: Verification of arithmetic functions with binary moment diagrams. In: Des Autom Conf, pp. 535-541, 1995
28. Bryant, R.E., Chen, Y.-A.: Verification of arithmetic circuits using binary moment diagrams. Software Tools Technol Transfer (this issue)
29. Burch, J.R.: Using BDDs to verify multipliers. In: Des Automat Conf, pp. 408-412, 1991
30. 20 states and beyond. Inf Comput 98(2): 142-170, 1992
31. Butler, K.M., Ross, D.E., Kapur, R.K., Mercer, M.R.: Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams. In: Des Autom Conf, pp. 417-420, 1991
32. Chen, Y.-A., Bryant, R.E.: PHDD: an efficient graph representation for floating point circuit verification. In: Int Conf CAD, pp. 2-7, 1997
33. Clarke, E., Fujita, M., McGeer, P., McMillan, K.L., Yang, J., Zhao, X.: Multi terminal binary decision diagrams: An efficient data structure for matrix representation. In: Int Workshop Logic Synth, pp. P6a: 1-15, 1993
34. Clarke, E.M., Fujita, M., Zhao, X.: Hybrid decision diagrams - overcoming the limitations of MTBDDs and BMDs. In: Int Conf CAD, pp. 159-163, 1995
35. Clarke, E.M., Zhao, X.: Word level symbolic model checking - a new approach for verifying arithmetic circuits. Technical Report CMU-CS-95-161, 1995
36. Coudert, O.: Two-level logic minimization: an overview. Integration, VLSI J 17(2): 97-140, 1994
37. Coudert, O., Berthet, C., Madre, J.C.: Verification of sequential machines using Boolean functional vectors. In: Proc IFIP Int Workshop Applied Formal Methods Correct VLSI Des, pp. 111-128, 1989
38. Coudert, O., Fraisse, H., Madre, J.C.: A breakthrough in two-level logic minimization. In: Int Workshop Logic Synth, p. P2b, 1993
39. Cyrluk, D., M̈oller, O., Rueb, H.: An efficient decision procedure for the theory of fixed-sized bitvectors. In: Comput Aided Verification. LNCS 1254. Berlin, Heidelberg, New York: Springer-Verlag, 1997
40. Drechsler, R.: BiTeS: a BDD based test pattern generator for strong robust path delay faults. In: Eur Des Autom Conf, pp. 322-327, 1994
41. Drechsler, R.: Formal verification of circuits. Kluwer Academic, Boston, Mass., USA, 2000
42. Drechsler, R., Becker, B.: Binary decision diagrams - theory and implementation. Kluwer Academic, Boston, Mass., USA,1998
43. Drechsler, R., Becker, B., Gockel, N.: A genetic algorithm for variable ordering of OBDDs. IEE Proc 143(6): 364-368, 1996
44. Drechsler, R., Becker, B., Jahnke, A.: On variable ordering and decomposition type choice in OKFDDs. In: IEEE Trans Comp 47(12), December 1998
45. Drechsler, R., Becker, B., Ruppertz, S.: KBMDs: a new data structure for verification. In: Eur Des Test Conf, pp. 2-8, 1996
46. Drechsler, R., Becker, B., Ruppertz, S.: The KBMD: a verification data structure. IEEE Des Test Comp, pp. 51-59, 1997
47. Drechsler, R., Drechsler, N., Gunther, W.: Fast exact minimization of BDDs. In: Des Autom Conf, pp. 200-205, 1998
48. Drechsler, R., Gunther, W.: Using lower bounds during dynamic BDD minimization. In: Des Autom Conf, pp. 29-32, 1999
49. Drechsler, R., Höreth, S.: Manipulation of *BMDs. In: ASP Des Autom Conf, pp. 433-438, 1998
50. Drechsler, R., Sarabi, A., Theobald, M., Becker, B., Perkowski, M.A.: Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams. In: Des Autom Conf, pp. 415-419, 1994
51. Drechsler, R., Sauerhoff, M., Sieling, D.: The complexity of the inclusion operation on OFDDs. IEEE Trans CAD 17(5): 457-459, 1998
52. Drechsler, R., Theobald, M., Becker, B.: Fast OFDD based minimization of fixed polarity Reed-Muller expressions. In: European Des Autom Conf, pp. 2-7, 1994
53. Enders, R.: Note on the complexity of binary moment diagram representations. IFIP WG 10.5 Workshop Appl Reed-Muller Expansion Circuit Des, pp. 191-197, 1995
54. Fortune, S., Hopcroft, J., Schmidt, E.M.: The complexity of equivalence and containment for free single variable program schemes. In: Int Colloquium Automat Lang Comput. LNCS 62. Berlin, Heidelberg, New York: Springer-Verlag, 1997, pp. 227-240
55. Friedman, S.J., Supowit, K.J.: Finding the optimal variable ordering for binary decision diagrams. IEEE Trans Comp 39(5): 710-713, 1990
56. Fujii, H., Ootomo, G., Hori, C.: Interleaving based variable ordering methods for ordered binary decision diagrams. In: Int Conf CAD, pp. 38-41, 1993
57. Fujita, M., Fujisawa, H., Kawato, N.: Evaluation and improvements of Boolean comparison method based on binary decision diagrams. In: Int Conf CAD, pp. 2-5, 1988
58. Fujita, M., Matsunaga, Y., Kakuda, T.: On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. In: Eur Conf Des Autom, pp. 50-54, 1991
59. Garey, M.R., Johnson, D.S.: Computers and intractability - a guide to the theory of NP-completeness. Freemann, San Francisco, 1979
60. Gergov, J.: Time-space tradeoffs for integer multiplication on various types of input oblivious sequential machines. Inf Process Lett 51: 265-269, 1994
61. Gergov, J., Meinel, C.: Efficient analysis and manipulation of OBDD's can be extended to FBDD's. IEEE Trans Comp 43: 1197-1209, 1994
62. Gergov, J., Meinel, C.: Mod-2-OBDD's - a data structure that generalizes EXOR-sum-of-products and ordered binary decision diagrams. Formal Methods Syst Des 8: 273-282, 1996
63. Gunther, W., Drechsler, R.: Linear transformations and exact minimization of BDDs. In: Great Lakes Symp VLSI, pp. 325-330, 1998
64. Gunther, W., Drechsler, R.: Minimization of free BDDs. In: ASP Des Autom Conf, 1999
65. Gunther, W., Drechsler, R.: On the computational power of linearly transformed BDDs. Inf Process Lett 119-125(75), 2000
66. Gunther, W., Drechsler, R.: Implementation of read-k-times BDDs on top of standard BDD packages. In: VLSI Design Conf, pp. 173-178, 2001
67. Gunther, W., Drechsler, R., Höreth, S.: Efficient dynamic minimization of word-level DDs based on lower bound computation. In: Int Conf Comp Des, pp. 383-388, 2000
68. Hachtel, G., Somenzi, F.: Logic synthesis and verification algorithms. Kluwer Academic, Boston, Mass., USA 1996
69. Harlow, J., Brglez, F.: Design of experiments and evaluation of BDD ordering heuristics. Software Tools Technol Transfer, (this issue)
70. Hett, A., Drechsler, R., Becker, B.: MORE: Alternative implementation of BDD packages by multi-operand synthesis. In: Eur Des Autom Conf, pp. 164-169, 1996
71. Höreth, S.: Compilation of optimized OBDD-algorithms. In: Eur Des Autom Conf, pp. 152-157, 1996
72. Höreth, S.: A word-level graph manipulation package. Software Tools Technol Transfer, (this issue)
73. Höreth, S., Drechsler, R.: Dynamic minimization of word-level decision diagrams. In: Des Autom Test Eur, pp. 612-617, 1998
74. Höreth, S., Drechsler, R.: Formal verification of word-level specifications. In: Des Autom Test Eur, pp. 52-58, 1999
75. Hromkovǐc, J.: Communication complexity and parallel computing. Berlin, Heidelberg, New York: Springer-Verlag, 1997
76. Ibarra, O.H., Kim, C.E.: Fast approximation algorithms for the knapsack and sum of subset problems. J ACM 22: 463-468, 1975
77. Ishiura, N., Sawada, H., Yajima, S.: Minimization of binary decision diagrams based on exchanges of variables. In: Int Conf CAD, pp. 472-475, 1991
78. Jain, J., Bitner, J.B., Abadir, M.S., Abraham, J.A., Fussell, D.: Indexed BDDs: algorithmic advances in techniques to represent and verify Boolean functions. IEEE Trans Comp 46: 1230-1245, 1997
79. Jeong, S.-W., Kim, T.-S., Somenzi, F.: An efficient method for optimal BDD ordering computation. In: Int Conf VLSI CAD, pp. 252-256, 1993
80. Jeong, S.-W., Plessier, B.F., Hachtel, G.D., Somenzi, F.: Variable ordering and selection for FSM traversal. In: Int Conf CAD, pp. 476-479, 1991
81. Kebschull, U., Rosenstiel, W.: Efficient graph-based computation and manipulation of functional decision diagrams. In: Eur Conf Des Autom, pp. 278-282, 1993
82. Kebschull, U., Schubert, E., Rosenstiel, W.: Multilevel logic synthesis based on functional decision diagrams. In: Eur Conf Des Autom, pp. 43-47, 1992
83. Kral, D.: Algebraic and uniqueness properties of parity ordered binary decision diagrams and their generalization. In: Symp Math Found Comp Sci. LNCS 1873. Berlin, Heidelberg, New York: Springer-Verlag, 2000, pp. 477-487
84. Krause, M.: Untere Schranken f̈ur Berechnungen durch Verzweigungsprogramme. PhD thesis, Humboldt Universiẗat Berlin, 1988. (in German)
85. Krause, M.: Lower bounds for depth-restricted branching programs. Inf Comput 91: 1-14, 1991
86. Krieger, R.: PLATO: a tool for computation of exact signal probabilities. In: VLSI Des Conf, pp. 65-68, 1993
87. Krieger, R., Becker, B., Keim, M.: A hybrid fault simulator for synchronous sequential circuits. In: Int Test Conf, pp. 614-623, 1994
88. Krieger, R., Becker, B., Sinkovic, R.: A BDD-based algorithm for computation of exact fault detection probabilities. In: Int Symp Fault-Tolerant Comp, pp. 186-195, 1993
89. Kuehlmann, A., Krohm, F.: Equivalence checking using cuts and heaps. In: Des Autom Conf, pp. 263-268, June 1997
90. Kushilevitz, E., Nisan, N.: Communication complexity. Cambridge University, Cambridge, UK, 1997
91. Lai, Y.-T., Pedram, M., Vrudhula, S.B.K.: BDD based decomposition of logic functions with application to FPGA synthesis. In: Des Autom Conf, pp. 642-647, 1993
92. Lai, Y.-T., Pedram, M., Vrudhula, S.B.K.: EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans CAD 13(8): 959-975, 1994
93. Lai, Y.-T., Sastry, S.: Edge-valued binary decision diagrams for multi-level hierarchical verification. In: Des Autom Conf, pp. 608-613, 1992
94. Lee, C.Y.: Representation of switching circuits by binary decision diagrams. Bell Syst Tech J 38: 985-999, 1959
95. L̈obbing, M., Sieling, D., Wegener, I.: Parity OBDDs cannot be handled efficiently enough. Inf Process Lett 67: 163-168, 1998
96. L̈obbing, M., Wegener, I.: The number of knight's tours equals 33,439,123,484,294 - counting with binary decision diagrams. Electron J Combin 3: R5, 1996
97. Malik, S., Wang, A.R., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Logic verification using binary decision diagrams in a logic synthesis environment. In: Int Conf CAD, pp. 6-9, 1988
98. McMillan, K.L.: Symbolic Model Checking. Kluwer Academic, Boston, Mass., USA 1993
99. Meinel, C., Slobodova, A.: On the complexity of constructing optimal ordered binary decision diagrams. In: Symp Math Found Comp Sci. LNCS 841. Berlin, Heidelberg, New York: Springer-Verlag, 1994, pp. 515-524
100. Meinel, C., Slobodova, A.: A unifying theoretical background for some BDD-based data structures. Formal Meth Syst Des 11: 223-237, 1997
101. Meinel, C., Somenzi, F., Theobald, T.: Linear sifting of decision diagrams. In: Des Autom Conf, pp. 202-207, 1997
102. Meinel, C., Theobald, T.: Algorithms and data structures in VLSI design: OBDD - foundations and applications. Berlin, Heidelberg, New York: Springer-Verlag
103. Mercer, M.R., Kapur, R., Ross, D.E.: Functional approaches to generating orderings for efficient symbolic representations. In: Des Autom Conf, pp. 624-627, 1992
104. Minato, S.: Zero-suppressed BDDs for set manipulation in combinatorial problems. In: Des Autom Conf, pp. 272-277, 1993
105. Minato, S.: Binary decision diagrams and applications for VLSI CAD. Kluwer, Boston, Mass., USA, 1996
106. Minato, S.: Fast factorization for implicit cube set representation. IEEE Trans CAD 15: 377-384, 1996
107. Minato, S.: Zero-suppressed BDDs and their applications. Software Tools Technol Transfer, (this issue)
108. Minato, S., Ishiura, N., Yajima, S.: Shared binary decision diagram with attributed edges for efficient Boolean function manipulation. In: Des Autom Conf, pp. 52-57, 1990
109. Mohnke, J., Molitor, P., Malik, S.: Application of BDDs in Boolean matching techniques for formal logic combinatorial verification. Software Tools Technol Transfer, (this issue)
110. Moret, B.M.E.: Decision trees and diagrams. Comput Surv 14: 593-623, 1982
111. Ochi, H., Ishiura, N., Yajima, S.: Breadth-first manipulation of SBDD of Boolean functions for vector processing. In: Des Autom Conf, pp. 413-416, 1991
112. Ochi, H., Yasuoka, K., Yajima, S.: Breadth-first manipulation of very large binary decision diagrams. In: Int Conf CAD, pp. 48-55, 1993
113. Razborov, A.A.: Lower bounds for deterministic and nonde-terministic branching programs. In: Fundam Comput Theor. LNCS 529. Berlin, Heidelberg, New York: Springer-Verlag, 1991, pp. 47-60
114. Ross, D.E., Butler, K.M., Kapur, R., Mercer, M.R.: Fast functional evaluation of candidate OBDD variable orderings. In: Eur Conf Des Autom, pp. 4-10, 1991
115. Rudell, R.: Dynamic variable ordering for ordered binary decision diagrams. In: Int Conf CAD, pp. 42-47, 1993
116. Savícky, P., Wegener, I.: Efficient algorithms for the transformation between different types of binary decision diagrams. Acta Inform 34: 245-256, 1997
117. Scholl, C., Becker, B., Weis, T.M.: Word-level decision diagrams, WLCDs and division. Technical Report 102, Albert-Ludwigs-University, Freiburg, In: Int. Conf. on Computer Aided Design, pp. 672-677, 1998
118. Scholl, C., Molitor, P.: Efficient ROBDD based computation of common decomposition functions of multioutput Boolean functions. In: Saucier, G., Mignotte, A. (eds.): Novel approaches in logic and architecture synthesis, pp. 57-63. Chapman & Hall, London, 1995
119. Sieling, D.: The nonapproximability of OBDD minimization. Inf Comput (to appear)
120. Sieling, D.: The complexity of minimizing FBDDs. In: Symp Math Found Comp Sci. LNCS 1672. Berlin, Heidelberg, New York: Springer-Verlag, 1999, pp. 251-261
121. Sieling, D.: Lower bounds for linear transformed OBDDs and FBDDs. In: Conf Found Software Technol Theor Comput Sci. LNCS 1738. Berlin, Heidelberg, New York: Springer-Verlag, 1999, pp. 356-368
122. Sieling, D., Wegener, I.: A comparison of free BDDs and transformed BDDs. Formal Meth Syst Des (to appear)
123. Sieling, D., Wegener, I.: NC-algorithms for operations on binary decision diagrams. Parallel Process Lett 3(1): 3-12, 1993
124. Sieling, D., Wegener, I.: Reduction of OBDDs in linear time. Inf Process Lett 48(3): 139-144, 1993
125. Sieling, D., Wegener, I.: Graph driven BDDs - a new data structure for Boolean functions. Theor Comput Sci 141: 283-310, 1995
126. Somenzi, F.: Efficient manipulation of decision diagrams. Software Tools Technol Transfer, (this issue)
127. Stanion, T., Bhattacharya, D.: TSUNAMI: a path oriented scheme for algebraic test generation. In: Int Symp Fault-Tolerant Comp, pp. 36-43, 1991
128. Tafertshofer, P., Pedram, M.: Factored edge-valued binary decision diagrams. Formal Meth Syst Des 10(2): 243-270, 1997
129. Tani, S., Hamaguchi, K., Yajima, S.: The complexity of the optimal variable ordering problems of shared binary decision diagrams. In: 4th Int Symp Algorithms Comput. LNCS 762. Berlin, Heidelberg, New York: Springer-Verlag, 1993, pp. 389-398
130. Tani, S., Imai, H.: A reordering operation for an ordered binary decision diagram and an extended framework for combinatorics of graphs. In: 5th Int Symp Algorithms Comput. LNCS 834. Berlin, Heidelberg, New York: Springer-Verlag, 1994, pp. 575-583
131. Thathachar, J.S.: On the limitations of ordered representations of functions. In: Comput Aided Verif. LNCS 1427. Berlin, Heidelberg, New York: Springer-Verlag, 1998, pp. 232-243
132. Touati, H.J., Savoj, H., Lin, B.: Implicit state enumeration of finite state machines using BDDs. In: Int Conf CAD, pp. 130-133, 1991
133. Waack, S.: On the descriptive and algorithmic power of parity ordered binary decision diagrams. In: 14th Symp Theor Aspects Comp Sci. LNCS 1200. Berlin, Heidelberg, New York: Springer-Verlag, 1997, pp. 201-212
134. Wegener, I.: The complexity of Boolean functions. Wiley, New York, and B.G. Teubner, Stuttgart, 1987
135. Wegener, I.: Branching programs and binary decision diagrams - theory and applications. SIAM Monogr Discrete Math Appl, 2000
136. Werchner, R., Harich, T., Drechsler, R., Becker, B.: Satisfiability problems for ordered functional decision diagrams. In: Sasao, T., Fujita, M. (eds.): Representations of discrete functions, pp. 233-248. Kluwer Academic, Boston, Mass., USA 1996
137. Wurth, B., Eckl, K., Antreich, K.: Functional multiple-output decomposition: Theory and implicit algorithm. In: Des Autom Conf, pp. 54-59, 1995
138. Yang, B., Chen, Y., Bryant, R., O'Hallaron, D.: Space and time efficient BDD construction via working set control. In: ASP Des Autom Conf, pp. 423-432, 1998