Formal verification of LTL formulas for systemc designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Große, Daniel ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; GATES (TRANSISTOR);

LINEAR TEMPORAL LOGIC (LTL);

LOGIC DESIGN;

EID: 0038082058     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. R. Drechsler and D. Große. Reachability analysis for formal verification of SystemC. In Euromicro Symposium on Digital System Design (DSD'2002), pages 337-340, 2002.
2. F. Ferrandi, M. Rendine, and D. Scuito. Functional verification for SystemC descriptions using constraint solving. In Design, Automation and Test in Europe, pages 744-751, 2002.
3. K.L. McMillan. Symbolic Model Checking. Kluwer Academic Publisher, 1993.
4. R. Drechsler (moderator). IEEE design and test roundtable on formal verification: current use and future perspectives. IEEE Design & Test of Comp., pages 105-113, 2002. Sept-Oct.
5. R. Gupta (moderator). IEEE design and test roundtable on C++-based design. IEEE Design & Test of Comp., pages 115-123, 2001. May-June.
6. J. Ruf, D. W. Hoffmann, T. Kropf, and W. Rosenstiel. Simulation-guided property checking based on multi-valued ar-automata. In Design, Automation and Test in Europe, pages 742-748, 2001.
7. Synopsys Inc., CoWare Inc., and Frontier Design Inc., http://www.systemc.org. Functional Specification for SystemC 2.0.
8. P.P. Williams, A. Biere, E.M. Clarke, and A. Gupta. Combining decision diagrams and SAT procedures for efficient symbolic model checking. In Computer Aided Verification, volume 1855 of LNCS, pages 124-138. Springer Verlag, 2000.