RTL-datapath verification using integer linear programming

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 741-746

  Brinkmann, R ^a   Drechsler, R ^b  

^a SIEMENS AG   (Germany)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN; EMBEDDED SYSTEMS; FORMAL LOGIC; HARDWARE; INTEGER PROGRAMMING; MATHEMATICAL TRANSFORMATIONS; MULTIPROCESSING SYSTEMS; PROBLEM SOLVING; RECONFIGURABLE HARDWARE; SEMANTICS;

ARITHMETIC PROPERTY; BOOLEAN SAT SOLVERS; INTEGER LINEAR PROGRAMMING; LINEAR ARITHMETIC CONSTRAINTS; LINEAR CONSTRAINT SOLVER; LINEAR CONSTRAINTS; ORDERS OF MAGNITUDE; REGISTER TRANSFER LEVEL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 84962325965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995022     Document Type: Conference Paper

References (18)

1. A. Biere, A. Cimatti, E. Clarke, M. Fujita, and Y. Zhu. Symbolic Model Checking Using SAT Procedures instead of BDDs. In Proceedings of DAC'99, pages 317-320, 1999.
2. J. R. L. Clark W. Barrett, David L. Dill. A decision procedure for bit-vector arithmetic. In Proceedings of DAC'98, pages 522-527, 1998.
3. D. Cyrluk, H. Rueß, and O. Möller. An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors. In Proceedings of 9th CAV'97, volume 1254 of Lecture Notes in Computer Science, pages 60-71, 1997.
4. G. B. Dantzig and B. C. Eaves. Fourier-Motzkin Elimination and Its Dual. Journal of Combinatorial Theory (A), 14:288-297, 1973.
5. R. Drechsler. Formal Verification of Circuits. Kluwer Academic Publisher, 2000.
6. F. Fallah. Coverage Directed Validation of Hardware Models. PhD thesis, MIT, 1999.
7. F. Fallah, S. Devadas, and K. Keutzer. Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. In Proceedings of 35th DAC-98, pages 528-533, 1998.
8. C.-Y. Huang and K.-T. Cheng. Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques. In Proceedings of DAC'00, pages 118-123, 2000.
9. P. Johannsen. BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction. In Proceedings of CAV'01 Conference, volume 2102 of Lecture Notes in Computer Science, pages 373-376, 2001.
10. M. O. Möller and H. Rueß. Solving Bit-Vector Equations. In Proceedings of 2nd FMCAD'98, volume 1522 of Lecture Notes in Computer Science, pages 36-48, 1998.
11. M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an Efficient SAT Solver. In Proceedings of DAC'01, pages 530-535, 2001.
12. W. Pugh. The Omega test: a fast and practical integer programming algorithm for dependence analysis. In Proceedings of the ACM, number 8, pages 102-114, 1992.
13. W. Pugh and D. Wonnacott. Experiences with constraint-based array dependence analysis. Technical report, University of Maryland, College Park, MD, 1994.
14. A. Schrijver. Theory of Linear and Integer Programming. John Wiley and Sons, 1998.
15. T. R. Shiple, J. H. Kukula, and R. K. Ranjan. A comparison of Presburger engines for EFSM reachability. In Proceedings of 10th CAV'98, volume 1427 of Lecture Notes in Computer Science, pages 280-292, 1998.
16. M. N. Velev and R. E. Bryant. Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. In Proceedings of DAC'01, pages 226-231, 2001.
17. P. Wolper and B. Boigelot. An Automata-Theoretic Approach to Presburger Arithmetic Constraints. In Proceedings of the SAS'95, volume 983 of Lecture Notes in Computer Science, pages 21-32. Springer-Verlag, 1995.
18. Z. Zeng, P. Kalla, and M. Ciesielski. LPSAT: A Unified Approach to RTL Satisfiability. In Proceedings of DATE'01 Conference, pages 398-402, 2001.