Logic verification based on diagnosis techniques

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 93-98

  Veneris, A ^a   Smith, A ^a   Abadir, M S ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; FORMAL LOGIC; RECONFIGURABLE HARDWARE;

CIRCUIT LINE; CONTROLLABILITY AND OBSERVABILITIES; DIAGNOSIS TECHNIQUES; FALSE NEGATIVES; GENERAL NATURE; LOGIC DIAGNOSIS; LOGIC FUNCTIONS; LOGIC VERIFICATION;

LOGIC CIRCUITS;

EID: 84954460948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1194999     Document Type: Conference Paper

References (19)

1. E. J. Aas, K. Klingsheim and T. Steen, "Quantifying design quality: a model and design experiments," in Proc. of EURO-ASIC, pp. 172-177, 1992.
2. M. S. Abadir, J. Ferguson and T. E. Kirkland, "Logic Verification Via Test Generation," in IEEE Trans. on Computer-Aided Design, vol. 7, pp. 138-148, January 1988.
3. D. Brand, "Verification of large synthesized designs," in Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 534-539, 1993.
4. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," in IEEE Trans. on Computers, vol. C-35, no. 8, pp. 677-691, 1986.
5. H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms," in IEEE Trans. on Computers, vol. C-32, no. 12, December 1983.
6. E. Goldberg, M. Prasad and R. Brayton, "Using SAT for Combinational Equivalence Checking," in Proc. of IEEE Design and Test in Europe (DATE), pp. 114-121, 2001.
7. J. Jain, A. Narayan, M. Fujita and A. Sangiovanni-Vincentelli, "A Survey of Techniques for Formal Verification of Combinational Circuits," in IEEE Int'l Conf. on Computer-Aided Design, pp. 445-454, 1997.
8. A. Kuehlmann and F. Krohm, "Equivalence checking using cuts and heaps," in Proc. of IEEE Design Automation Conference, pp. 263-267, 1997.
9. W. Kunz and D. K. Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems-Test, Verification, and Optimization," in IEEE Trans. on Computer-Aided Design, vol. 13, no. 9, pp. 1143-1158 September 1994.
10. W. Kunz, "HANNIBAL: An Efficient Tool for Logic Verification Based on Recursive Learning," in IEEE Int'l Conf. on Computer-Aided Design, pp. 538-543, 1993.
11. W. Kunz, D. K. Pradhan and S. M. Reddy, "A Novel Framework for Logic Verification in a Synthesis Environment," in IEEE Trans. on Computer-Aided Design, vol. 15, no. 1, pp. 20-32 September 1996.
12. Y. Matsunaga, "An efficient equivalence checker for combinational circuits," in Proc. IEEE Design Automation Conference, pp. 629-634, 1996.
13. D. Paul, M. Chatterjee and D. K. Pradhan, "VERILAT: Verification Using Logic Augmentation and Transformations," in IEEE Trans. on Computer-Aided Design, vol. 19, no. 9 pp. 1041-1051, 2001.
14. S. Ravi, I. Ghosh, V. Boppana and N. K. Jha, "A Technique for identifying RTL and gate-level correspondences," in IEEE Int'l Conf. on Computer Design, pp. 591-594, 2000.
15. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization," in Proc. of Int'l Conference on Computer Design, pp. 328-333, 1992.
16. Synopsys "Design Compiler," available from http://www.synopsys.com/products/logic/design-compiler.html, 2002
17. A. Veneris, and I. N. Hajj, "Design Error Diagnosis and Correction Via Test Vector Simulation," in IEEE Trans. on Computer-Aided Design,vol. 18, no. 12, pp. 1803-1816, December 1999.
18. A. Veneris, M. S. Abadir and I. Ting, "Design Rewiring based on Diagnosis Techniques," in Proc. of IEEE Asia and South Pacific Design Automation Conf., pp. 479-484, 2001.
19. A. Veneris and M. S. Abadir, "Design Rewiring Using ATPG," in IEEE Trans. on Computer-Aided Design, in press.